MPC8544COMEDEV Freescale Semiconductor, MPC8544COMEDEV Datasheet - Page 93

• Manufacturer Part Number: MPC8544COMEDEV
• Description: KIT DEV EXPRESS MPC8544COM
• Manufacturer: Freescale Semiconductor
• Type: MPUr

Specifications of MPC8544COMEDEV

• Contents: Board
• For Use With/related Products: MPC8544
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

19 Clocking
This section describes the PLL configuration of the MPC8544E. Note that the platform clock is identical
to the core complex bus (CCB) clock.
19.1
Table 63
specifications for the memory bus.
19.2
The CCB clock is the clock that drives the e500 core complex bus (CCB), and is also called the platform
clock. The frequency of the CCB is set using the following reset signals (see
Freescale Semiconductor
e500 core processor frequency
Notes:
1. Caution: The CCB to SYSCLK ratio and e500 core to CCB ratio settings must be chosen such that the resulting SYSCLK
2. The minimum e500 core frequency is based on the minimum platform frequency of 333 MHz.
Memory bus clock speed
Notes:
1. Caution: The CCB clock to SYSCLK ratio and e500 core to CCB clock ratio settings must be chosen such that the resulting
2. The memory bus speed is half of the DDR/DDR2 data rate, hence, half of the platform clock frequency.
SYSCLK frequency, e500 (core) frequency, and CCB clock frequency do not exceed their respective maximum or minimum
operating frequencies. Refer to
settings.
frequency, e500 (core) frequency, and CCB frequency do not exceed their respective maximum or minimum operating
frequencies. Refer to
•
•
Characteristic
SYSCLK input signal
Binary value on LA[28:31] at power up
provides the clocking specifications for the processor cores and
Clock Ranges
CCB/SYSCLK PLL Ratio
MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
Section 19.2, “CCB/SYSCLK PLL Ratio,”
Characteristic
Table 63. Processor Core Clocking Specifications
Section 19.2, “CCB/SYSCLK PLL Ratio,”
Min
667
Table 64. Memory Bus Clocking Specifications
667 MHz
Max
667
Maximum Processor Core Frequency
Min
667
800 MHz
Max
800
and
Section 19.3, “e500 Core PLL Ratio,”
Min
667
1000 MHz
Maximum Processor Core
667, 800, 1000, 1067 MHz
and
Min
166
1000
Max
Section 19.3, “e500 Core PLL Ratio,”
Frequency
Table 64
Min
667
1067 MHz
Table
Max
266
1067
Max
provides the clocking
65):
MHz
MHz
Unit
for ratio settings.
Unit
for ratio
Notes
Notes
Clocking
1, 2
1, 2
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