MPC8379E-MDS-PB Freescale Semiconductor, MPC8379E-MDS-PB Datasheet

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... Technical Data MPC8379E PowerQUICC II Pro Processor Hardware Specifications This document provides an overview of the MPC8379E PowerQUICC II Pro processor features, including a block diagram showing the major functional components. The device is a cost-effective, low-power, highly integrated host processor that addresses the requirements of several printing ...

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... The optional security engine (SEC 3.0) is noted with the extension “E” at the end. It allows CPU-intensive cryptographic operations to be offloaded from the main CPU core. The security-processing accelerator provides hardware acceleration for the DES, 3DES, AES, SHA-1, and MD-5 algorithms. MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev MPC8379E ...

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... In addition to the security engine, a new high-speed interface, such as SATA, is included. the differences between MPC837xE derivatives and provides the number of ports available for each interface. Table 1. High-Speed Interfaces on the MPC8377E, MPC8378E, and MPC8379E Descriptions SGMII PCI Express® SATA 1.1 DDR Memory Controller The DDR1/DDR2 memory controller includes the following features: • ...

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... The device provides an integrated four-channel DMA controller with the following features: • Allows chaining (both extended and direct) through local memory-mapped chain descriptors (accessible by local masters) • Supports misaligned transfers MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev DUART, Enhanced Local Bus Controller Freescale Semiconductor ...

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... Single 32-bit data PCI interface operates MHz • PCI 3.3-V compatible (not 5-V compatible) • Support for host and agent modes • On-chip arbitration, supporting 5 external masters on PCI • Selectable hardware-enforced coherency MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4 Freescale Semiconductor Overview 5 ...

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... Electrical Characteristics This section provides the AC and DC electrical specifications and thermal characteristics for the MPC8379E. The device is currently targeted to these specifications. Some of these specifications are independent of the I/O cell, but are included for a more complete reference. These are not purely I/O buffer design specifications ...

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... IN REF the PCI interface may overshoot/undershoot according to the PCI Electrical Specification for 3.3-V operation shown in Figure 2. 6 L[1,2]_nV includes SDAV _0, XCOREV DD DD MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4 Freescale Semiconductor Table 2. Absolute Maximum Ratings Symbol and OV DD ...

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... direction. 2 L[1,2]_nV , SDAV _0, XCOREV DD DD MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev 667 MHz 800 MHz up to 667 MHz 800 MHz 2 C, and up to 667 MHz L[1,2]_nV 800 MHz commerical ...

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... C, JTAG, SPI, and USB GPIO signals 1 Specialized SerDes output capabilities are described in the relevant section of the specification (such as SATA) MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4 Freescale Semiconductor Not to Exceed 10% of tinterface1 refers to the clock period associated with the bus clock interface. ...

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... DD The opposite sequence applies to the power down requirements. The I/O supplies must go down first and immediately followed by the core and PLL supplies. 3 Power Characteristics The estimated typical power dissipation for the MPC8379E device is shown in Core Frequency CSB/DDR Frequency (MHz) (MHz) 333 ...

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... Typical power is based on a voltage of V 800 MHz, and running a Dhrystone benchmark application. 4 Maximum power is based on a voltage 800 MHz, worst case process, and running an artificial smoke test. MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4 Freescale Semiconductor 1 (continued) Sleep Power Typical Application ...

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... MHz, 0.09 32-bit 133 MHz, 0.07 32-bit Local Bus I/O 83 MHz, 0.05 Load = 32-bit MHz, 0.04 32-bit 50 MHz, 0.03 32-bit MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev /LBV (2.5 V) (3.3 V) (3.3 V) (2.5 V) 0.35 — — — 0.49 — ...

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... Clock Input Timing This section provides the clock input DC and AC electrical characteristics for the MPC8379E. Note that the PCI_CLK/PCI_SYNC_IN signal or CLKIN signal is used as the PCI input clock depending on whether the device is configured as a host or agent device. CLKIN is used when the device is in host mode. ...

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... PHY device can tolerate the duty cycle generated by the eTSEC GTX_CLK. See Section 8.2.2, “RGMII and RTBI AC Timing reference clock. MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev Table 8. CLKIN AC Timing Specifications Symbol Min ...

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... Input setup time for POR config signals (CFG_RESET_SOURCE[0:3], CFG_CLKIN_DIV, and CFG_LBMUX) with respect to negation of PORESET when the device is in PCI agent mode Input hold time for POR config signals with respect to negation of HRESET MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4 Freescale Semiconductor Symbol Condition V — ...

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... PCI_SYNC_IN. When the device is In PCI host mode the primary PCI_SYNC_IN clock is applied to the CLKIN input, and PCI_SYNC_IN period depends on the value of CFG_CLKIN_DIV. See the MPC8379E Integrated Host Processor Reference Manual for more details. ...

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... MV . This rail should track variations in the DC level of MV REF 4 Output leakage is measured with all outputs disabled See AN3665, “MPC837xE Design Checklist,” for proper DDR termination. MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4 Freescale Semiconductor Symbol Min I 13 all times. ...

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... AC input high voltage Table 19 provides the input AC timing specifications for the DDR1 SDRAM when GV Table 19. DDR1 SDRAM Input AC Timing Specifications for 2.5-V Interface Parameter AC input low voltage AC input high voltage MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev (typ Symbol Min C IO ...

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... MHz data rate MCSn output hold with respect to MCK 400 MHz data rate 333 MHz data rate 266 MHz data rate 200 MHz data rate MCK to MDQS skew MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4 Freescale Semiconductor Symbol Min t CISKEW –500 – ...

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... DQSS override bits in the TIMING_CFG_2 register. This will typically be set to the same delay as the clock adjust in the CLK_CNTL register. The timing parameters listed in the table assume that these 2 parameters have been set to the same adjustment value. See the MPC8379E PowerQUICC II Pro Host Processor Reference Manual for a description and understanding of the timing modifications enabled by use of these bits. ...

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... DDKHMH Figure 5 shows the DDR1 and DDR2 SDRAM output timing diagram. MCK[n] MCK[n] ADDR/CMD Write A0 MDQS[n] MDQ[x] Figure 5. DDR1 and DDR2 SDRAM Output Timing Diagram MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4 Freescale Semiconductor MCK[n] MCK[n] t MCK t DDKHMHmax) = 0.6 ns MDQS t DDKHMH(min) = –0.6 ns MDQS Figure 4 ...

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... Maximum baud rate Oversample rate Notes: 1 Actual attainable baud rate will be limited by the latency of interrupt processing. 2 The middle of a start bit is detected as the 8 th sampled each 16 sample. MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev Ω Figure 6. DDR AC Test Load Symbol Min ...

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... DD1 IN DD2 Input low current (V = GND) IN Note supports eTSEC 1. DD1 LV supports eTSEC 2. DD2 MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4 Freescale Semiconductor Ethernet: Enhanced Three-Speed Ethernet (eTSEC) Table 25 are based on a 2.5 V CMOS interface voltage as Symbol Min LV 3.13 DD1 LV DD2 V 2.40 ...

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... MII transmit AC timing specifications. Table 26. MII Transmit AC Timing Specifications At recommended operating conditions with LV Parameter TX_CLK clock period 10 Mbps TX_CLK clock period 100 Mbps TX_CLK duty cycle TX_CLK to MII data TXD[3:0], TX_ER, TX_EN delay MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev Symbol Min LV 2.37 DD1 LV ...

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... Input low voltage Input high voltage RX_CLK clock period 10 Mbps RX_CLK clock period 100 Mbps RX_CLK duty cycle RXD[3:0], RX_DV, RX_ER setup time to RX_CLK RXD[3:0], RX_DV, RX_ER hold time to RX_CLK MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4 Freescale Semiconductor of 3.3 V ± 5 Symbol t ...

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... RGMII and RTBI AC timing specifications. Table 28. RGMII and RTBI AC Timing Specifications At recommended operating conditions with LV Parameter Data to clock output skew (at transmitter) Data to clock input skew (at receiver) Clock period MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev 3.3 V ± 5 Symbol t MRXR ...

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... This symbol represents the external EC_GTX_CLK125 and does not follow the original signal naming convention. Figure 10 provides the AC test load for eTSEC. Output MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4 Freescale Semiconductor Ethernet: Enhanced Three-Speed Ethernet (eTSEC) of 2.5 V ± 5 Symbol ...

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... The RMII transmit AC timing specifications are in Table 29. RMII Transmit AC Timing Specifications At recommended operating conditions with LV Parameter REF_CLK clock period REF_CLK duty cycle REF_CLK peak-to-peak jitter Rise time REF_CLK (20%–80%) MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev RGTH t SKRGT TXD[8:5] TXD[3:0] TXD[7:4] ...

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... Parameter/Condition Input low voltage at 3 Input high voltage at 3 REF_CLK clock period REF_CLK duty cycle REF_CLK peak-to-peak jitter Rise time REF_CLK (20%–80%) Fall time REF_CLK (80%–20%) MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4 Freescale Semiconductor of 3.3 V ± 5 Symbol t RMTF t RMTDX (first two letters of functional block)(signal)(state) (reference)(state) for outputs ...

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... Management Interface Electrical Characteristics The electrical characteristics specified here apply to MII management interface signals MDIO (management data input/output) and MDC (management data clock). Figure 15 provides the AC test load for eTSEC. Output MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev 3.3 V ± 5%. DD Symbol t ...

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... Table 33. MII Management AC Timing Specifications Parameter MDC frequency MDC period MDC clock pulse width high MDC to MDIO valid MDC to MDIO delay MDIO to MDC setup time MDIO to MDC hold time MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4 Freescale Semiconductor Table 31 and Conditions Symbol — LV DD1 ...

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... MII management AC timing diagram. MDC MDIO (Input) MDIO (Output) Figure 16. MII Management Interface Timing Diagram 9 USB This section provides the AC and DC electrical characteristics for the USB dual-role controllers. MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev Symbol Min Typical t — MDCR t — ...

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... For active/float timing measurements, the high impedance or off state is defined to be when the total current delivered through the component pin is less than or equal to that of the leakage current specification. MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4 Freescale Semiconductor Table 34. USB DC Electrical Characteristics ...

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... Output high voltage I = –4 Output low voltage I OL Input high voltage Input low voltage Input high current Input low current MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev Ω Figure 17. USB AC Test Load t USIVKH t USKHOX Figure 18. USB Interface Timing Diagram provide the DC electrical characteristics for the local bus interface. ...

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... LALE output fall to LAD output transition (LATCH hold time) LALE output fall to LAD output transition (LATCH hold time) LALE output fall to LAD output transition (LATCH hold time) Local bus clock to LALE rise Local bus clock to output valid (except LALE) MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4 Freescale Semiconductor = 2 Conditions — ...

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... LBCR[AHD] is not set and the load on LALE output pin equals to the load on LAD output pins. LBOTOT3 8 For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev Symbol t ...

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... For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. Figure 19 provides the AC test load for the local bus. Output MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4 Freescale Semiconductor 1 Symbol t ...

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... Input Signal: LGTA Output Signals: LSDA10/LSDWE/LSDRAS/ LSDCAS/LSDDQM[0:3] LA[27:31]/LBCTL/LBCKE/LOE Output (Data) Signals: LAD[0:31]/LDP[0:3] Output (Address) Signal: LAD[0:31] LALE Figure 20. Local Bus Signals, Non-special Signals Only (PLL Enable Mode) MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev LBIVKH t LBIVKH t LBKHOX t LBKHOV t LBKHOZ ...

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... LGTA Output Signals: LSDA10/LSDWE/LSDRAS/ LSDCAS/LSDDQM[0:3] LA[27:31]/LBCTL/LBCKE/LOE Output (Data) Signals: LAD[0:31]/LDP[0:3] Output (Address) Signal: LAD[0:31] LALE Figure 21. Local Bus Signals, Non-special Signals Only (PLL Bypass Mode) MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4 Freescale Semiconductor t LBIVKH t LBKHOV t LBKHOZ t LBKHOV t LBKHOZ ...

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... Input Signals: LAD[0:31]/LDP[0:3] UPM Mode Output Signals: LCS[0:7]/LBS[0:1]/LGPL[0:5] Output (Data) Signals: LAD[0:31]/LDP[0:3] Output (Address) Signal: LAD[0:31] Figure 22. Local Bus Signals, GPCM/UPM Signals for LCRR[CLKDIV (PLL Enable Mode) MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev LBKHOV LBKHOX t LBIVKH t ...

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... LAD[0:31]/LDP[0:3] UPM Mode Output Signals: LCS[0:7]/LBS[0:1]/LGPL[0:5] Output (Data) Signals: LAD[0:31]/LDP[0:3] Output (Address) Signal: LAD[0:31] Figure 23. Local Bus Signals, GPCM/UPM Signals for LCRR[CLKDIV (PLL Bypass Mode) MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4 Freescale Semiconductor t LBKHOZ t LBKHOV t LBIVKH ...

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... Input Signals: LAD[0:31] UPM Mode Output Signals: LCS[0:7]/LBS[0:1]/LGPL[0:5] Output (Data) Signals: LAD[0:31]/LDP[0:3] Output (Address) Signal: LAD[0:31] Figure 24. Local Bus Signals, GPCM/UPM Signals for LCRR[CLKDIV (PLL Enable Mode) MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev LBKHOZ t LBKHOV t LBIVKH t LBIVKH ...

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... SD_DAT[0:3]/CMD as outputs and sample the SD_DAT[0:3] as inputs. This behavior is true for both full- and high-speed modes. Note that this is a non-standard implementation, as the SD card specification assumes that in high-speed mode, data is driven at the rising edge of the clock. MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4 Freescale Semiconductor Enhanced Secure Digital Host Controller (eSDHC) t ...

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... SD_CLK clock frequency—full speed mode SD_CLK clock cycle SD_CLK clock frequency—identification mode SD_CLK clock low time SD_CLK clock high time SD_CLK clock rise and fall times Input setup times: SD_CMD, SD_DATx, SD_CD to SD_CLK MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev Symbol Condition V — — ...

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... For reference only, according to the SD card specifications. 4 Average, for reference only. Figure 26 provides the eSDHC clock input timing diagram. eSDHC External Clock operational mode Figure 26. eSDHC Clock Input Timing Diagram MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4 Freescale Semiconductor = 3.3 V ± 165 mV Symbol t SFSIXKH t ...

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... DATA_DELAY CLK_DELAY 11.2.1.2 Full-Speed Write Meeting Hold (Minimum Delay) The following equations show how to calculate the allowed skew range between the SD_CLK and SD_DAT/CMD signals on the PCB. t CLK_DELAY MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev (Clock Cycle) SFSCK Driving Edge t SFSKHOV ...

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... Full-Speed Read Meeting Setup (Maximum Delay) The following equations show how to calculate the allowed combined propagation delay range of the SD_CLK and SD_DAT/CMD signals on the PCB. t CLK_DELAY CLK_DELAY MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4 Freescale Semiconductor + t t < – IH SFSKHOX SFSCKL DATA_DELAY < ...

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... Input hold times: SD_CMD, SD_DATx, SD_CD to SD_CLK Output delay time: SD_CLK to SD_CMD, SD_DATx valid Output Hold time: SD_CLK to SD_CMD, SD_DATx invalid SD_CLK delay within device SD Card Input Setup SD Card Input Hold SD Card Output Valid MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev > DATA_DELAY = 3.3 V ± ...

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... Average, for reference only. Figure 29 provides the eSDHC clock input timing diagram. eSDHC External Clock operational mode Figure 29. eSDHC Clock Input Timing Diagram MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4 Freescale Semiconductor = 3.3 V ± 165 mV Symbol t OH (first three letters of functional block)(signal)(state) ...

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... This means that data delay should be equal or less than the clock delay in the ideal case where ns: SHSCLKL t t – DATA_DELAY CLK_DELAY t t – DATA_DELAY CLK_DELAY MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev (Clock Cycle) SHSCK Driving Edge t CLK_DELAY SHSKHOV t SHSCKL SHSKHOX t ...

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... Note that the internal clock which is guaranteed to be 50% duty cycle is used to sample the data, and therefore used in the equations. MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4 Freescale Semiconductor < t ...

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... The following equation is the combined formula to calculate the propagation delay range of the SD_CLK and SD_DAT/CMD signals on the PCB. × 0 – SHSCK OH SHSIXKH 12 JTAG This section describes the DC and AC electrical specifications for the IEEE 1149.1 (JTAG) interface of the MPC8379E. MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev DATA_DELAY ODLY SHSIVKH × < 1 – ...

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... JTAG external clock rise and fall times TRST assert time Input setup times: Boundary-scan data Input hold times: Boundary-scan data Valid times: Boundary-scan data Output hold times: Boundary-scan data MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4 Freescale Semiconductor Symbol Condition V — — — ...

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... Figure 32. AC Test Load for the JTAG Interface Figure 33 provides the JTAG clock input timing diagram. JTAG External Clock Figure 33. JTAG Clock Input Timing Diagram Figure 34 provides the TRST timing diagram. TRST MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev Symbol t JTKLDZ TDO t JTKLOZ (first two letters of functional block)(signal)(state) (reference)(state) for outputs ...

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... JTAG External Clock TDI, TMS t JTKLOX TDO TDO Output Data Valid Figure 36. Test Access Port Timing Diagram MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4 Freescale Semiconductor VM t JTDVKH t JTKLDV t JTKLDZ VM = Midpoint Voltage (OVDD/2) Figure 35. Boundary-Scan Timing Diagram ...

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... Output voltage (open drain or open collector) condition = 3 mA sink current capacitance of one bus line in pF Refer to the MPC8379E PowerQUICC II Pro Integrated Host Processor Reference Manual for information on the digital filter used. 4 I/O pins will obstruct the SDA and SCL lines 13.2 ...

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... For rise and fall times, the latter convention is used with the appropriate letter: R (rise (fall). 2 MPC8379E provides a hold time of at least 300 ns for the SDA signal (referred to the V undefined region of the falling edge of SCL. 3 ...

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... This section describes the general AC timing parameters of the PCI bus of the device. Note that the PCI_CLK/PCI_SYNC_IN or CLKIN signal is used as the PCI input clock depending on whether the MPC8379E is configured as a host or agent device. CLKIN is used when the device is in host mode. Table 49 shows the PCI AC timing specifications at 66 MHz ...

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... Input timings are measured at the pin. 5 PCI specifications allows 2 ns skew for 33 MHz but includes the total allowed skew, board, connectors, etc. 6 Value does not comply with the PCI 2.3 Local Bus Specifications. MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4 Freescale Semiconductor , VIH = 0.7 × ...

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... Figure 41. PCI Output AC Timing Measurement Condition 15 Serial ATA (SATA) This section describes the DC and AC electrical specifications for the serial ATA (SATA) of the MPC8379E. Note that the external cabled applications or long backplane applications (Gen1x and Gen2x) are not supported. MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev Ω ...

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... SATA reference clock timing waveform. Ref_CLK Figure 42. SATA Reference Clock Timing Waveform 15.2 Transmitter (Tx) Output Characteristics This section discusses the Gen1i/1.5G and Gen2i/3G transmitter output characteristics for the SATA interface. MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4 Freescale Semiconductor Table Condition Symbol Min — ...

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... DC characteristics for the SATA interface at Gen2i or 3.0 Gbits/s transmission. Table 54. Gen 2i/3G Transmitter DC Specifications Parameter Tx differential output voltage Tx differential pair impedance Note: 1 Terminated by 50 Ω load. MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev Symbol Min V 400 SATA_TXDIFF Z 85 ...

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... Gen1i or 1.5 Gbits/s differential receiver input DC characteristics for the SATA interface. Table 56. Gen1i/1.5G Receiver Input DC Specifications Parameter Differential input voltage Differential Rx input impedance Note: 1 Voltage relative to common of either signal comprising a differential pair. MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4 Freescale Semiconductor Symbol Min t — CH_SPEED T 333.2 ...

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... Table 59. Gen 2i/3G Receiver AC Specifications Parameter Channel Speed Unit Interval Total jitter /10 C3dB BAUD Total jitter /500 C3dB BAUD Total jitter /1667 C3dB BAUD MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev Symbol Min T 666.4333 UI U — SATA_TXTJ5UI U — SATA_TXTJ250UI U — SATA_TXDJ5UI U — SATA_TXDJ250UI Symbol Min V ...

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... Note: 1 Measured at Tx output pins peak to peak phase variation, random data pattern. 16 Timers This section describes the DC and AC electrical specifications for the timers of the MPC8379E. 16.1 Timers DC Electrical Characteristics Table 60 provides the DC electrical characteristics for the device timers pins, including TIN, TOUT, TGATE, and RTC_CLK ...

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... GPIO Figure 43 provides the AC test load for the timers. Output 17 GPIO This section describes the DC and AC electrical specifications for the GPIO of the MPC8379E. 17.1 GPIO DC Electrical Characteristics Table 62 provides the DC electrical characteristics for the device GPIO. Table 62. GPIO DC Electrical Characteristics This specification applies when operating at 3.3 V ± 165 mV supply. ...

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... IPIC inputs and outputs are asynchronous to any visible clock. IPIC outputs should be synchronized before use by any external synchronous logic. IPIC inputs are required to be valid for at least t in edge triggered mode. 19 SPI This section describes the DC and AC electrical specifications for the SPI of the MPC8379E. MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4 Freescale Semiconductor = 50 Ω ...

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... Output Figure 46 through Figure 47 represent the AC timing from generally reference the rising edge of the clock, these AC timing diagrams also apply when the falling edge is the active edge. MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev Table 66. SPI DC Electrical Characteristics Condition Symbol — V — ...

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... Note: The clock edge is selectable on SPI. Figure 47. SPI AC Timing in Master Mode (Internal Clock) Diagram 20 High-Speed Serial Interfaces (HSSI) The MPC8379E features two serializer/deserializer (SerDes) interfaces to be used for high-speed serial interconnect applications. See Table 1 This section describes the common portion of SerDes DC electrical specifications, which is the DC requirement for SerDes reference clocks. The SerDes data lane’ ...

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... Sometimes it may be even different between the receiver input and driver output circuits within the same component also referred as the DC offset in some occasion. MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev volts. This is also referred as each signal wire’s – ...

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... Each differential clock input (SDn_REF_CLK or SDn_REF_CLK) has a 50 Ω termination to SGND_SRDSn (xcorevss) followed by on-chip AC-coupling. — The external reference clock driver must be able to drive this termination. MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4 Freescale Semiconductor Differential Swing, VID or VOD = A – B Differential Peak Voltage, VDIFFp = |A – B| Differential Peak-Peak Voltage, VDIFFpp = 2 × ...

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... The input amplitude of the differential clock must be between 400 mV and 1600 mV differential peak-peak (or between 200 mV and 800 mV differential peak). In other words, each signal wire of the differential pair must have a single-ended swing less than 800 mV and MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev Ω ...

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... AC-coupled into the unused phase (SDn_REF_CLK) through the same source impedance as the clock input (SDn_REF_CLK) in use. SDn_REF_CLK SDn_REF_CLK Figure 50. Differential Reference Clock Input DC Requirements (External DC-Coupled) MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4 Freescale Semiconductor the maximum average current requirements sets the Figure 51 200 mV < Input Amplitude or Differential Peak < 800 mV High-Speed Serial Interfaces (HSSI) Section 20.2.1, “ ...

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... LVPECL outputs can produce signal with too large amplitude and may need to be DC-biased at clock driver output first, then followed with series attenuation resistor to reduce the amplitude, in addition to AC-coupling. MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev 400 mV < SDn_REF_CLK Input Amplitude < 800 mV ...

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... SerDes reference clock connection reference circuits for LVDS type clock driver. Since LVDS clock driver’s common-mode voltage is higher than the device SerDes reference clock input’s allowed range (100 to 400 mV), AC-coupled connection scheme must be used. It assumes the LVDS MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4 Freescale Semiconductor NOTE below are for conceptual reference only ...

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... For example, if the LVPECL output’s differential peak is 900 mV and the desired SerDes reference clock input amplitude is selected as 600 mV, the attenuation factor is 0.67, which requires Ω. Please consult MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev SDn_REF_CLK 100 Ω ...

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... Phase noise less than 100 KHz can be tracked by the PLL and data recovery loops and is less of a problem. Phase noise above 15 MHz is filtered by the PLL. The most problematic phase noise MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4 Freescale Semiconductor ...

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... Minus SDn_REF_CLK Figure 57. Differential Measurement Points for Rise and Fall Time SDn_REF_CLK V CROSS MEDIAN SDn_REF_CLK Figure 58. Single-Ended Measurement Points for Rise and Fall Time Matching MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev 1.0 V ± 5%. DD_SRDS DD_SRDS Symbol Rise Edge Rate Fall Edge Rate ...

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... The package parameters are provided in the following list. The package type × 31 mm, 689 plastic ball grid array (TePBGA II). Package outline Interconnects Pitch Module height (typical) Solder Balls Ball diameter (typical) MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4 Freescale Semiconductor SD1_RXn or SD1_TXn or SD2_RXn SD2_TXn 50 Ω 50 Ω ...

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... Dimensioning and tolerancing per ASME Y14. 5M-1994. 3 Maximum solder ball diameter measured parallel to Datum A. 4 Datum A, the seating plane, is determined by the spherical crowns of the solder balls. 5 Parallelism measurement should exclude any effect of mark on top surface of package. MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev Freescale Semiconductor ...

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... MA5 MA6 MA7 MA8 MA9 MA10 MA11 MA12 MA13 MA14 MBA0 MBA1 MBA2 MCAS_B MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4 Freescale Semiconductor Table 69. TePBGA II Pinout Listing Package Pin Number Clock Signals K24 C10 N24 L24 M24 M25 M26 L26 AF11 ...

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... MCK2 MCK3 MCK4 MCK5 MCKE0 MCKE1 MCS_B0 MCS_B1 MCS_B2 MCS_B3 MDIC0 MDIC1 MDM0 MDM1 MDM2 MDM3 MDM4 MDM5 MDM6 MDM7 MDM8 MDQ0 MDQ1 MDQ2 MDQ3 MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev Package Pin Number AA1 AB2 AB1 AH8 AJ8 B6 B2 ...

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... MDQ8 MDQ9 MDQ10 MDQ11 MDQ12 MDQ13 MDQ14 MDQ15 MDQ16 MDQ17 MDQ18 MDQ19 MDQ20 MDQ21 MDQ22 MDQ23 MDQ24 MDQ25 MDQ26 MDQ27 MDQ28 MDQ29 MDQ30 MDQ31 MDQ32 MDQ33 MDQ34 MDQ35 MDQ36 MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4 Freescale Semiconductor Package Pin Number ...

Page 84

... MDQ53 MDQ54 MDQ55 MDQ56 MDQ57 MDQ58 MDQ59 MDQ60 MDQ61 MDQ62 MDQ63 MDQS0 MDQS1 MDQS2 MDQS3 MDQS4 MDQS5 MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev Package Pin Number Y5 AA4 AB6 AD3 AC4 AD4 AF1 AE4 AC5 AE2 AE3 AG1 AG2 AG3 AF5 ...

Page 85

... MECC7 MODT0 MODT1 MODT2 MODT3 MRAS_B MVREF1 MVREF2 MWE_B UART_SIN1/ MSRCID2/LSRCID2 UART_SOUT1/ MSRCID0/LSRCID0 UART_CTS_B[1]/ MSRCID4/LSRCID4 UART_RTS_B1 UART_SIN2/ MSRCID3/LSRCID3 UART_SOUT2/ MSRCID1/LSRCID1 UART_CTS_B[2]/ MDVAL/LDVAL UART_RTS_B[2] MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4 Freescale Semiconductor Package Pin Number AH1 AJ3 AA3 DUART Interface L28 ...

Page 86

... LA11/LAD16 LA12/LAD17 LA13/LAD18 LA14/LAD19 LA15/LAD20 LA16/LAD21 LA17/LAD22 LA18/LAD23 LA19/LAD24 LA20/LAD25 LA21/LAD26 LA22/LAD27 LA23/LAD28 LA24/LAD29 LA25/LAD30 LA26/LAD31 LA27 MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev Package Pin Number E24 G28 H25 F26 C26 J28 F21 F23 E25 E26 A23 F24 G24 F25 ...

Page 87

... LA8/LCS_B7/LDP3 LFCLE/LGPL0 LFALE/LGPL1 LFRE_B/LGPL2/LOE_B LFWP_B/LGPL3 LGPL4/LFRB_B/LGTA_B/ LUPWAIT/LPBSE LA9/LGPL5 LSYNC_IN LSYNC_OUT LWE_B0/LFWE0/LBS_B0 LWE_B1/LFWE1/LBS_B1 LWE_B2/LFWE2/LBS_B2 LWE_B3/LFWE3/LBS_B3 TSEC1_COL/GPIO2[20] TSEC1_CRS/GPIO2[21] MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4 Freescale Semiconductor Package Pin Number C29 E28 B26 J25 H29 A22 B22 C23 B23 D25 F19 C27 D24 ...

Page 88

... TSEC1_TXD3/ CFG_RESET_SOURCE[3] EC_GTX_CLK125 EC_MDC/CFG_CLKIN_DIV EC_MDIO TSEC2_COL/GPIO1[21]/ TSEC1_TMR_TRIG1 TSEC2_CRS/GPIO1[22]/ TSEC1_TMR_TRIG2 TSEC2_GTX_CLK TSEC2_RX_CLK/ TSEC1_TMR_CLK TSEC2_RX_DV/GPIO1[23] TSEC2_RX_ER/GPIO1[25] TSEC2_RXD0/GPIO1[16] TSEC2_RXD1/GPIO1[15] TSEC2_RXD2/GPIO1[14] MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev Package Pin Number AJ25 AG22 AD19 AD20 AD22 AE21 AE22 AD21 AJ22 AG23 AH22 AD23 AE23 AF23 ...

Page 89

... GPIO1[6]/GTM1_TIN3/ GTM2_TIN4/DREQ2_B GPIO1[7]/GTM1_TGATE3_B/ GTM2_TGATE4_B/DACK2_B GPIO1[8]/GTM1_TOUT3_B/ DDONE2_B GPIO1[9]/GTM1_TIN4/ GTM2_TIN3/DREQ3_B GPIO1[10]/GTM1_TGATE4_B/ GTM2_TGATE3_B/DACK3_B GPIO1[11]/GTM1_TOUT4_B/ GTM2_TOUT3_B/DDONE3_B MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4 Freescale Semiconductor Package Pin Number AH25 AG28 AJ26 AG26 AH28 AF27 AJ28 AF29 GPIO1 Interface P25 ...

Page 90

... USBDR_D3_SPEED/GPIO2[3] USBDR_D4_DP/GPIO2[4] USBDR_D5_DM/GPIO2[5] USBDR_D6_SER_RCV/ GPIO2[6] USBDR_D7_DRVVBUS/ GPIO2[7] IIC1_SCL IIC1_SDA IIC2_SCL IIC2_SDA TCK TDI TDO TMS TRST_B MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev Package Pin Number USB/GPIO2 Interface AJ11 AG12 AJ10 AF10 AE9 AG13 AH12 AG10 AF13 AG11 AH11 AG9 AF9 ...

Page 91

... PCI_AD16 PCI_AD17 PCI_AD18 PCI_AD19 PCI_AD20 PCI_AD21 PCI_AD22 PCI_AD23 PCI_AD24 PCI_AD25 PCI_AD26 PCI_AD27 PCI_AD28 PCI_AD29 PCI_AD30 MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4 Freescale Semiconductor Package Pin Number PCI Signals P26 N28 P29 P27 R26 R29 T24 T25 R27 P28 U25 R28 ...

Page 92

... PCI_REQ_B0 PCI_REQ_B[1]/CPCI_HS_ES PCI_REQ_B2 PCI_REQ_B3 PCI_REQ_B4 PCI_RESET_OUT_B PCI_SERR_B PCI_STOP_B PCI_TRDY_B M66EN Programmable Interrupt Controller (PIC) Interface MCP_OUT_B IRQ_B0/MCP_IN_B/GPIO2[12] IRQ_B1/GPIO2[13] MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev Package Pin Number AE24 T26 T28 V29 Y29 U28 V27 AE27 AC28 AD27 AC27 AE25 ...

Page 93

... L1_SD_RXA_P L1_SD_RXE_N L1_SD_RXE_P L1_SD_TXA_N L1_SD_TXA_P L1_SD_TXE_N L1_SD_TXE_P L1_SDAVDD_0 L1_SDAVSS_0 L1_XCOREVDD L1_XCOREVSS AG14, AG15, AG16, AH16, AG18, AG20 L1_XPADVDD MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4 Freescale Semiconductor Package Pin Number F10 D9 C9 AE10 AD10 AD9 PMC Interface D13 SerDes1 Interface AJ14 ...

Page 94

... L2_SD_RXE_P L2_SD_TXA_N L2_SD_TXA_P L2_SD_TXE_N L2_SD_TXE_P L2_SDAVDD_0 L2_SDAVSS_0 L2_XCOREVDD L2_XCOREVSS L2_XPADVDD L2_XPADVSS SPICLK/SD_CLK SPIMISO/SD_DAT0 SPIMOSI/SD_CMD SPISEL_B/SD_CD MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev Package Pin Number AF14, AE17, AF20 SerDes2 Interface C19 C15 B17 A17 A19 B19 A15 B15 D18 E18 D15 ...

Page 95

... W18, L19, M19, N19, P19, T19, U19, V19, W19, AC20, G21, AF21, C22, J23, AA23, AJ23, B24, W24, AF24, K25, R25, AD25, D26, G27, M27, T27, Y27, AB27, AG27, A29, MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4 Freescale Semiconductor Package Pin Number AD12 ...

Page 96

... This pin must always be tied to OVDD. 15 Open or tie to GND. 16 Voltage settings are dependent on the frequency used; see 17 See AN3665, “MPC837xE Design Checklist,” for proper eTSEC termination. MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev Package Pin Number AD13 Power for e300 core PLL (1.0 V F13 Power for eLBC PLL (1 ...

Page 97

... Clocking Figure 61 shows the internal distribution of clocks within the MPC8379E. System PLL CFG_CLKIN_DIV CLKIN The primary clock source for the device can be one of two inputs, CLKIN or PCI_CLK, depending on whether the device is configured in PCI host or PCI agent mode. When the device is configured as a PCI host device, CLKIN is its primary input clock. CLKIN feeds the PCI clock divider (÷ ...

Page 98

... SPMF and COREPLL fields in the reset configuration word low register (RCWLR) which is loaded at power-on reset or by one of the hard-coded reset options. See Chapter 4, “Reset, Clocking, and Initialization,” in the MPC8379E Reference Manual for more information on the clock subsystem. ...

Page 99

... If either RCWLR[DDRCM] or RCWLR[LBCM] are set, the system PLL VCO frequency = 2 × (CSB frequency) × (System PLL VCO Divider). The VCO divider needs to be set properly so that the System PLL VCO frequency is in the range of 400–800 MHz. MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4 Freescale Semiconductor Minimum Operating 1 ...

Page 100

... Reset High 0010 High 0011 High 0100 High 0101 High 0110 MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4 100 Table 72. System PLL Multiplication Factors The LBIUCM, DDRCM, and SPMF parameters in the reset Table 73. System PLL VCO Divider csb_clk : 2 Input Clock Ratio ...

Page 101

... Low 0111 Low 1000 Low 1001 Low 1010 Low 1011 Low 1100 Low 1101 Low 1110 Low 1111 MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4 Freescale Semiconductor Input Clock Frequency (MHz) csb_clk : 25 2 Input Clock Ratio 175 200 225 250 275 ...

Page 102

... MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4 102 shows the encodings for RCWLR[COREPLL]. COREPLL values NOTE Table 76. e300 Core PLL Configuration core_clk : csb_clk Ratio 6 0 PLL bypassed (PLL off, csb_clk clocks core directly) n n/a 0 ...

Page 103

... CSB frequencies less than 133 MHz will not support Gigabit Ethernet rates. 4 Minimum data rate for DDR2 is 250 MHz and for DDR1 is 167 MHz. 5 Applies to DDR2 only. 6 Applies to eLBC PLL-enabled mode only. MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4 Freescale Semiconductor core_clk : csb_clk Ratio 6 0 4:1 0 ...

Page 104

... An estimation of the chip junction temperature θ where: = junction temperature (° ambient temperature for the package (° junction to ambient thermal resistance (°C/W) θ JA MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4 104 × where I/O I/O , can be obtained from the equation: J × Symbol Value Unit ° ...

Page 105

... where junction temperature (° thermocouple temperature on top of package (°C) T MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4 Freescale Semiconductor – J NOTE × NOTE Ψ determine the junction temperature and a measure of the JT × ...

Page 106

... The heat sink choice is determined by the application environment (temperature, air flow, adjacent component power dissipation) and the physical space available. Because of the wide variety of application environments, a single standard heat sink applicable to all cannot be specified. MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4 106 θ ...

Page 107

... Heat sink vendors include the following: Aavid Thermalloy www.aavidthermalloy.com Alpha Novatech www.alphanovatech.com International Electronic Research Corporation (IERC) www.ctscorp.com Millennium Electronics (MEI) www.mei-thermal.com MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4 Freescale Semiconductor Thermal Resistance Air Flow Natural Convection 0.5 m/s 1 m/s 2 m/s 4 m/s Natural Convection 0 ...

Page 108

... From this case temperature, the junction temperature is determined from the junction to case thermal resistance θ where junction temperature (° case temperature of the package (°C) C MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4 108 × Freescale Semiconductor ...

Page 109

... PCB, utilizing short traces to minimize inductance. Capacitors may be placed directly under the device using a standard escape pattern. Others may surround the part. MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4 Freescale Semiconductor , and preferably these voltages will be derived directly from V ...

Page 110

... When data is held high, SW1 is closed (SW2 is open) and R OV /2. R then becomes the resistance of the pull-up devices other in value. Then MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4 110 2 C). is trimmed until the voltage at the pad equals P )/2. N OVDD R N Pad ...

Page 111

... For more information on required pull-up resistors and the connections required for the JTAG interface, see AN3665, “MPC837xE Design Checklist.” 25 Ordering Information Ordering information for the parts fully covered by this specification document is provided in Section 25.1, “Part Numbers Fully Addressed by This Document.” MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4 Freescale Semiconductor × ...

Page 112

... Part Numbers Fully Addressed by This Document Table 81 provides the Freescale part numbering nomenclature for the MPC8379E. Note that the individual part numbers correspond to a maximum processor core frequency. For available frequencies, contact your local Freescale sales office. In addition to the processor frequency, the part numbering scheme also includes an application modifier which may specify special application conditions ...

Page 113

... MPC8378 TePBGA II MPC8378E MPC8379 MPC8379E 25.2 Part Marking Parts are marked as in the example shown in Figure 64. Freescale Part Marking for TePBGA II Devices MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4 Freescale Semiconductor SVR Rev 1.0 Rev. 2.1 0x80C7_0010 0x80C7_0021 0x80C6_0010 0x80C6_0021 0x80C5_0010 ...

Page 114

... Frequency Options for Host Mode,” and Mode,” updated csb_clk frequencies available. • In Table 81, “Part Numbering Nomenclature,” removed footnote to “e300 core Frequency.” MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4 114 Table 84. Document Revision History Substantive Change(s) Characteristics,” ...

Page 115

... In Table 82, “Available Parts (Core/DDR Data Rate),” added new row for 800/400 MHz. 0 12/2008 Initial public release. MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4 Freescale Semiconductor Substantive Change(s) = 65°C (W)”. j ,” updated I REF Listing,” ...

Page 116

... Literature Distribution Center 1-800 441-2447 or +1-303-675-2140 Fax: +1-303-675-2150 LDCForFreescaleSemiconductor @hibbertgroup.com Document Number: MPC8379EEC Rev. 4 11/2010 Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document ...