MPC8379E-MDS-PB Freescale Semiconductor, MPC8379E-MDS-PB Datasheet - Page 98

• Manufacturer Part Number: MPC8379E-MDS-PB
• Description: BOARD PROCESSOR FOR MDS S
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC II™ PROr
• Type: MPUr

Specifications of MPC8379E-MDS-PB

• Contents: Board
• For Use With/related Products: MPC8379
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Clocking
As shown in
loop (PLL) and the clock unit to create the coherent system bus clock (csb_clk), the internal clock for the
DDR controller (ddr_clk), and the internal clock for the local bus interface unit (lbiu_clk).
The csb_clk frequency is derived from a complex set of factors that can be simplified into the following
equation:
In PCI host mode, PCI_SYNC_IN × (1 + CFG_CLKIN_DIV) is the CLKIN frequency.
The csb_clk serves as the clock input to the e300 core. A second PLL inside the e300 core multiplies up
the csb_clk frequency to create the internal clock for the e300 core (core_clk). The system and core PLL
multipliers are selected by the SPMF and COREPLL fields in the reset configuration word low register
(RCWLR) which is loaded at power-on reset or by one of the hard-coded reset options. See Chapter 4,
“Reset, Clocking, and Initialization,” in the MPC8379E Reference Manual for more information on the
clock subsystem.
The internal ddr_clk frequency is determined by the following equation:
Note that ddr_clk is not the external memory bus frequency; ddr_clk passes through the DDR clock divider
(÷2) to create the differential DDR memory bus clock outputs (MCK and MCK). However, the data rate
is the same frequency as ddr_clk.
The internal lbiu_clk frequency is determined by the following equation:
Note that lbiu_clk is not the external local bus frequency; lbiu_clk passes through the LBIU clock divider
to create the external local bus clock outputs (LCLK[0:2]). The eLBC clock divider ratio is controlled by
LCRR[CLKDIV].
Some of the internal units may be required to be shut off or operate at lower frequency than the csb_clk
frequency. Those units have a default clock ratio that can be configured by a memory mapped register after
the device comes out of reset.
1
98
eTSEC1, eTSEC2
eSDHC and I
Security block
USB DR
PCI and DMA complex
SATA1, 2, 3, 4
This only applies to I
2
C1
Figure
Unit
1
2
MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4
csb_clk = {PCI_SYNC_IN × (1 + CFG_CLKIN_DIV)} × SPMF
61, the primary clock input (frequency) is multiplied up by the system phase-locked
C1 (I
2
C2 clock is not configurable).
ddr_clk = csb_clk × (1 + RCWLR[DDRCM])
lbiu_clk = csb_clk × (1 + RCWLR[LBCM])
Table 70
Table 70. Configurable Clock Units
Default Frequency
specifies which units have a configurable clock frequency.
csb_clk/3
csb_clk/3
csb_clk/3
csb_clk/3
csb_clk/3
csb_clk
Off, csb_clk, csb_clk/2, csb_clk/3
Off, csb_clk, csb_clk/2, csb_clk/3
Off, csb_clk, csb_clk/2, csb_clk/3
Off, csb_clk
Off, csb_clk, csb_clk/2, csb_clk/3
Off, csb_clk, csb_clk/2, csb_clk/3
Options
Freescale Semiconductor
Eqn. 20
Eqn. 21
Eqn. 22