MPC8379E-MDS-PB Freescale Semiconductor, MPC8379E-MDS-PB Datasheet - Page 2

• Manufacturer Part Number: MPC8379E-MDS-PB
• Description: BOARD PROCESSOR FOR MDS S
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC II™ PROr
• Type: MPUr

Specifications of MPC8379E-MDS-PB

• Contents: Board
• For Use With/related Products: MPC8379
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Overview
2.0 dual-role controller, a programmable interrupt controller, dual I
controller, an enhanced secured digital host controller, and a general-purpose I/O port.
block diagram of the MPC8379E.
The following features are supported in the MPC8379E:
The optional security engine (SEC 3.0) is noted with the extension “E” at the end. It allows CPU-intensive
cryptographic operations to be offloaded from the main CPU core. The security-processing accelerator
provides hardware acceleration for the DES, 3DES, AES, SHA-1, and MD-5 algorithms.
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DMA
e300c4s core built on Power Architecture® technology with 32-Kbyte instruction cache and
32-Kbyte data cache, a floating point unit, and two integer units
DDR1/DDR2 memory controller supporting a 32/64-bit interface
Peripheral interfaces, such as a 32-bit PCI interface with up to 66-MHz operation
32-bit local bus interface running up to 133-MHz
USB 2.0 (full/high speed) support
Power management controller for low-power consumption
High degree of software compatibility with previous-generation PowerQUICC processor-based
designs for backward compatibility and easier software migration
Optional security engine provides acceleration for control and data plane security protocols
Security
MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4
PCI
Controller
Dual I
Interrupt
DUART
Timers
GPIO
SPI
Figure 1. MPC8379E Block Diagram and Features
2
C
Host
Hi-Speed
USB 2.0
Device
32-Kbyte
D-Cache
e300 Core
RGMII, RMII,
RTBI, MII
MPC8379E
eTSEC
32-Kbyte
I-Cache
RGMII, RMII,
RTBI, MII
eTSEC
2
C controllers, a 4-channel DMA
Enhanced
Local Bus
PHY
PHY
SATA
PHY
PHY
Freescale Semiconductor
Figure 1
DDR1/DDR2
Controller
SDRAM
Controller
SD/MMC
shows the