5.07.01 FLASHER ARM Segger Microcontroller Systems, 5.07.01 FLASHER ARM Datasheet - Page 45

• Manufacturer Part Number: 5.07.01 FLASHER ARM
• Description: PROGRAMMER JTAG FOR ARM CORES
• Manufacturer: Segger Microcontroller Systems
• Type: In-System Programmerr

Specifications of 5.07.01 FLASHER ARM

• Contents: Programmer
• For Use With/related Products: ARM7, ARM9, Cortex
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 899-1002

5.3
Flasher ARM (UM08007)
The TAP controller and ICE logic is reset independently from the ARM core with
nTRST (DBGnTRST on synthesizable cores). For the ARM core to operate correctly, it
is essential that both signals are asserted after power-up.
The advantage of having separate connection to the two reset signals is that it allows
the developer performing software debug to setup breakpoints, which are retained by
the ICE logic even when the core is reset. (For example, at address 0, to allow the
code to be single-stepped as soon as it comes out of reset). This can be particularly
useful when first trying to bring up a board with a new ASIC.
You may tie (DBG)nTRST to the core reset, but this removes some of the flexibility
and usefulness of the debug tools. What some designers who are facing similar pin
constraints have done is to implement some kind of reset circuit within their device.
This typically will assert both nTRST and the core reset for the initial power-on reset,
but subsequent 'warm' resets, where the power to the device is maintained, will
cause only the core reset to go LOW.
RESET, nTRST
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