EVAL-AD1895EB Analog Devices Inc, EVAL-AD1895EB Datasheet - Page 20

• Manufacturer Part Number: EVAL-AD1895EB
• Description: BOARD EVAL FOR AD1895
• Manufacturer: Analog Devices Inc
• Type: Sample Rate Converterr

Specifications of EVAL-AD1895EB

• Rohs Status: RoHS non-compliant
• Contents: Evaluation Board
• For Use With/related Products: AD1895

EVAL-AD1895EB
MODULE IF_Logic
TITLE 'AD1896 EVB Input Interface Logic'
//===================================================================================
// FILE:
// REVISION DATE: 03-20-01
// REVISION BY:
// REVISION:
//
// DESCRIPTION:
//
// This input interface PLD (U2) selects between the External Data Interface header
// (HDR3) and the on-board CS8414 DIR (U1) for the AD1896 ASRC input signals, depending
// upon the SPDIF/DDI switch position (S1). When the SPDIF Receiver DIR is the selected
// signal source the digital audio signals, SDATA_I, SCLK_I and LRCLK_I are derived from
// the DIR output. SPDIF receiver needs the digital data in the SPDIF format in order to
// generate these signals. When the external data is the selected source the digital
// signals from (HDR3) are applied to the AD1896.
// Signals SCLK_I, LRCLK_I, DDI_SCLK, DDI_LRCLK, DIR_SCLK, DIR_FSYNC on the PLD are
// bi-directional signals. The direction of these signals are controlled by the
// MASTER_SLAVE MODE switch position (S4). When the AD1896 input serial port is set in the
// master mode, the SCLK_I and LRCLK_I are generated from the AD1896 input serial port.
// On the other hand, these signals are provided from the external source in the slave mode
// operation.
// PLD also decodes the Input Interface Format Switch (S3) and sets the Interface mode pins
// for both the CS8414 DIR and the AD1896 ASRC.
//===================================================================================
LIBRARY 'MACH';
DECLARATIONS
// IF_Logic DEVICE 'M4-64/32-15VC';
"INPUTS ===========================================================================
// TDI, TCK, TMS
"OUTPUTS =========================================================================
// TDO
AD1896
//IO SIGNALS
FOR HDR3
ASRC
"NODES
//================================================================================
DIR_SDATA
SPDIF_DDI
DDI_SDATA
RESET
RESET_LO
MS_MODE2, MS_MODE1, MS_MODE0
M0, M1, M2, M3
SMODE_I_0, SMODE_I_1, SMODE_I_2
SDATA_I
DIR_FSYNC, DIR_SCLK
DDI_LRCLK, DDI_SCLK
LRCLK_I, SCLK_I
I_SDATA, ISCLK, ILRCLK
IN_MODE2,IN_MODE1,IN_MODE0
1.0
pin 29 istype 'com';
Chirag Patel
input_pld.abl
pin 4,7,26 istype 'com';
pin 1 istype 'com';
pin 12 istype 'com';
pin 22 istype 'com';
Pin 23 istype 'com';
Pin 44 istype 'com';
pin 37 istype 'com';
pin 35,36;
pin 24,25,30 istype 'com'; //MASTER/SLAVE MODE SWITCH S4
pin 33,32,31 istype 'com'; //INPUT SERIAL MODE FORMAT FOR
pin 18,15,14 istype 'com'; //INPUT SERIAL MODE SWITCH S3
pin 8,9,10,11 istype 'com'; //SPDIF_RVR MODE SELECT
pin 2,3;
pin 21,20;
node istype 'com';
in_pld.abl
in_pld.abl
//JTAG O/P
//CS8414 DIR SDATA OUT
//Active low reset input
//JTAG I/P's
//SPDIF_DDI SWITCH S1
//EXTERNAL DATA INPUT DDI
//Active hi reset output to AD1896
//DIR_FYSNC AND DIR_SCLK IO'S
//LRCLK_I AND SCLK_I IO'S TO AD1896
//SERIAL DATA INPUT TO AD1896 ASRC
//EXTERNAL LRCLK AND SCLK IO'S