EVAL-AD1895EB Analog Devices Inc, EVAL-AD1895EB Datasheet - Page 5

• Manufacturer Part Number: EVAL-AD1895EB
• Description: BOARD EVAL FOR AD1895
• Manufacturer: Analog Devices Inc
• Type: Sample Rate Converterr

Specifications of EVAL-AD1895EB

• Rohs Status: RoHS non-compliant
• Contents: Evaluation Board
• For Use With/related Products: AD1895

DEFAULT CONFIGURATION
The default configuration of this evaluation board is highlighted
in Tables VII and VIII. The AD1895 is configured in 24-bit
input and output data format, with input serial ports in slave
mode and output serial port in (768 × f
configuration, input serial port needs to be driven by an exter-
nal system, such as, Audio Precision for the slave mode
operation. An on-board third overtone crystal oscillator at
33.8688 MHz clocks the AD1895. Since the output serial port is
configured in 768 × f
by 33.8688 MHz clock, the output sample rate will be 44.1 kHz
for this configuration. The maximum input sample rate for this
case can be up to 192 kHz based on the requirement that the
AD1895 master clock must be higher than 138 times the
maximum input or output sample rate. The AD1895 can be
clocked by secondary on-board clock oscillator (U15) by first
inserting the desired clock oscillator in socket U15 and then
switching the clock source selection from on-board crystal to
clock oscillator (U15) by jumper JP4; however, the clock oscillator
Input
Mode
(S3)
LJ
I
RJ-24
RJ-20
RJ-18
RJ-16
2
S
Input Mode
(S3)
Position 0
LJ-24 Bits
X
Output
Mode
(JP1)
LJ-24
I
RJ-24
RJ-20
RJ-18
RJ-16
TDM
2
S-24
S
Output Mode
(JP1)
Position 1, 2, 3, 4
Shorted
LJ-24 Bits
master mode and the AD1895 is clocked
X
Both ports in
Not Used
I_MAS_768
Master/Slave
Mode (S4)
SLAVE mode
O_MAS_768
O_MAS_512
O_MAS_256
I_MAS_512
I_MAS_256
Table VIII. Default Evaluation Board Configuration
S
) master mode. In this
Master/Slave
Mode (S4)
Position 6
Output Port
Master,
768 f
Table VII. Default Jumper/Switch Settings
X
S_OUT
Input Source
(HDR3, HDR1,
J1, U4)
DIRECT
INPUT
TDM_IN
SPDIF
TOSLINK
Bypass Mode
(S6)
Enable
Disable
Sample
DAC Inter.
Ratio Select
(JP2)
Position 1, 2
Shorted
48 kHz
Rate
is enabled for SLAVE mode only (Switch S3 position 7). The evalu-
ation board contains 12.288 MHz (U15) clock oscillator. The
operating and quiescent currents for the ± 12 V dc supplies are
listed below.
X SPDIF
X Disable
+12 V Quiescent Current
–12 V Quiescent Current
+12 V Normal Operation Current
–12 V Normal Operation Current
Output
Source
(HDR2,
HDR5, J2)
DIRECT
OUTPUT
TDM_OUT
Automute
Enable (JP3)
Enable
AP1 TRANSMITTER
LRCLK
SDATA
Clock Source
(JP4)
Shorted
33.8688 MHz
Crystal Osc
Position 2, 3
SCLK
X
X
DAC Inter.
Ratio
Select
(JP2)
96/48
192/48
Mute
(S7)
Enable
Disable
SCLK_I
LRCLK_I
SDATA_I
AD1895
Bypass
Mode
(S6)
Pushed
Down
Off
LRCLK_O
SDATA_O
SCLK_O
EVAL-AD1895EB
X
X
X
~250 mA
~5 mA
~300 mA – 360 mA
~5 mA
Clock
Source
(JP4)
On-board
33.8688 MHz
Crystal
External
256
AP2 RECEIVER
Mute
(S7)
Pushed
Down
Off
SCLK
LRCLK
SDATA
f
S
Clock
X