EVAL-AD1895EB Analog Devices Inc, EVAL-AD1895EB Datasheet - Page 22

• Manufacturer Part Number: EVAL-AD1895EB
• Description: BOARD EVAL FOR AD1895
• Manufacturer: Analog Devices Inc
• Type: Sample Rate Converterr

Specifications of EVAL-AD1895EB

• Rohs Status: RoHS non-compliant
• Contents: Evaluation Board
• For Use With/related Products: AD1895

EVAL-AD1895EB
// AD1896 ASRC Input Serial port signals
(SPDIF_DDI));
(!SPDIF_DDI));
(SPDIF_DDI));
// Internal node signals
(!SPDIF_DDI))
(BOTH_SLAVE#MATCH_PHASE#O_MAS_768#O_MAS_512#O_MAS_256) & (SPDIF_DDI)))
(BOTH_SLAVE#MATCH_PHASE#O_MAS_768#O_MAS_512#O_MAS_256) & (SPDIF_DDI));
(!SPDIF_DDI))
(SPDIF_DDI))
"====================================================================================
END IF_Logic
//===================================================================================
MODULE
TITLE
//===================================================================================
// FILE:
// REVISION DATE:
// REVISION BY:
// REVISION:
// DESCRIPTION:
// This output interface PLD (U3) decodes output interface signals of AD1896 and sources
// these signals to the DAC, DIT and external header (HDR2, HDR5).
// Signals SCLK_O, LRCLK_O, DDO_SCLK and DDO_LRCLK on the PLD are bi-directional signals.
// The direction of these signals are controlled by the MASTER_SLAVE MODE switch position
(S4).
// When the AD1896 output serial port is set in the master mode, the SCLK_O and LRCLK_O are
// generated from the AD1896 output serial port. On the other hand, these signals are provided
// from the external source in the slave mode operation.
DIR_SCLK.oe
SCLK_I.oe
LRCLK_I.oe
DDI_SCLK
DDI_LRCLK
DIR_SCLK
DIR_FSYNC
SCLK_I
LRCLK_I
SDATA_I
ISCLK
ILRCLK = ((DDI_LRCLK) & (BOTH_SLAVE # MATCH_PHASE#O_MAS_768#O_MAS_512#O_MAS_256) &
I_SDATA = (DDI_SDATA & !SPDIF_DDI) # (DIR_SDATA & SPDIF_DDI);
IF_Logic
= ((DDI_SCLK) & (BOTH_SLAVE#MATCH_PHASE#O_MAS_768#O_MAS_512#O_MAS_256) &
# ((LJ#RJ24#RJ20) & ((DIR_SCLK) &
# ((SCLK_I) & (IN_MAS_768 # IN_MAS_512 # IN_MAS_256))
# ((I2S # RJ18 # RJ16) & (DIR_SCLK) &
# ((DIR_FSYNC) & (BOTH_SLAVE # MATCH_PHASE#O_MAS_768#O_MAS_512#O_MAS_256) &
# ((LRCLK_I) & (IN_MAS_768 # IN_MAS_512 # IN_MAS_256));
'AD1896 EVB Output Interface Logic'
= ((LJ # RJ24 # RJ20 # RJ18 # RJ16 # I2S) & (ISCLK) & (!SPDIF_DDI))
= ISCLK;
= ((!ISCLK) & (LJ # RJ24 # RJ20 # RJ18 # RJ16)) # (ISCLK & I2S);
= (SPDIF_DDI & DIR_FSYNC) # (((I2S & !DDI_LRCLK) # (!I2S & DDI_LRCLK)) &
= (DDI_SDATA & !SPDIF_DDI) # (((LJ#RJ24#RJ20#RJ18#RJ16#I2S)&(DIR_SDATA)) &
= (BOTH_SLAVE # MATCH_PHASE # O_MAS_768 # O_MAS_512 # O_MAS_256);
= (BOTH_SLAVE # MATCH_PHASE # O_MAS_768 # O_MAS_512 # O_MAS_256);
= ILRCLK;
= ILRCLK;
= (IN_MAS_768 # IN_MAS_512 # IN_MAS_256);
# ((((LJ # RJ24 # RJ20) & (!ISCLK)) # ((I2S # RJ18 # RJ16) & (ISCLK))) &
03-20-01
Chirag Patel
1.0
output_pld.abl
out_pld.abl