AD9518-3/PCBZ Analog Devices Inc, AD9518-3/PCBZ Datasheet - Page 40
![no-image](/images/manufacturer_photos/0/0/57/analog_devices_inc_sml.jpg)
AD9518-3/PCBZ
Manufacturer Part Number
AD9518-3/PCBZ
Description
BOARD EVAL FOR AD9518-3
Manufacturer
Analog Devices Inc
Specifications of AD9518-3/PCBZ
Main Purpose
Timing, Clock Generator
Utilized Ic / Part
AD9518-3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
AD9518-3
Asynchronous Reset via the RESET Pin
An asynchronous hard reset is executed by momentarily pulling
RESET low. A reset restores the chip registers to the default
settings.
Soft Reset via 0x00<5>
A soft reset is executed by writing 0x00<5> and 0x00<2> = 1b.
This bit is not self-clearing; therefore, it must be cleared by
writing 0x00<5> and 0x00<2> = 0b to reset it and complete the
soft reset operation. A soft reset restores the default values to
the internal registers. The soft reset bit does not require an
update registers command (0x232) to be issued.
POWER-DOWN MODES
Chip Power-Down via PD
The AD9518 can be put into a power-down condition by
pulling the PD pin low. Power-down turns off most of the
functions and currents inside the AD9518. The chip remains in
this power-down state until PD is brought back to Logic High.
When woken up, the AD9518 returns to the settings programmed
into its registers prior to the power-down, unless the registers
are changed by new programming while the PD pin is held low.
The PD power-down shuts down the currents on the chip,
except the bias current necessary to maintain the LVPECL
outputs in a safe shutdown mode. This is needed to protect the
LVPECL output circuitry from damage that could be caused by
certain termination and load configurations when tristated.
Because this is not a complete power-down, it can be called
sleep mode.
When the AD9518 is in a PD power-down, the chip is in the
following state:
• The PLL is off (asynchronous power-down).
• The VCO is off.
• The CLK input buffer is off.
• All dividers are off.
• All LVPECL outputs are in safe off mode.
• The serial control port is active, and the chip responds to
commands.
Rev. 0 | Page 40 of 64
If the AD9518 clock outputs must be synchronized to each
other, a SYNC is required upon exiting power-down (see the
Synchronizing the Outputs—SYNC Function section). A VCO
calibration is not required when exiting power-down.
PLL Power-Down
The PLL section of the AD9518 can be selectively powered
down. There are three PLL operating modes set by 0x10<1:0>,
as shown in Table 43.
In asynchronous power-down mode, the device powers down as
soon as the registers are updated.
In synchronous power-down mode, the PLL power-down is
gated by the charge pump to prevent unwanted frequency
jumps. The device goes into power-down on the occurrence of
the next charge pump event after the registers are updated.
Distribution Power-Down
The distribution section can be powered down by writing
0x230<1> = 1b. This turns off the bias to the distribution
section. If the LVPECL power-down mode is normal operation
(00b), it is possible for a low impedance load on that LVPECL
output to draw significant current during this power-down. If
the LVPECL power-down mode is set to 11b, the LVPECL
output is not protected from reverse bias and can be damaged
under certain termination conditions.
Individual Clock Output Power-Down
Any of the clock distribution outputs may be powered down
individually by writing to the appropriate registers. The register
map details the individual power-down settings for each output.
The LVPECL outputs have multiple power-down modes
(see Table 44), which give some flexibility in dealing with the
various output termination conditions. When the mode is set to
10b, the LVPECL output is protected from reverse bias to
2 VBE + 1 V. If the mode is set to 11b, the LVPECL output is
not protected from reverse bias and can be damaged under
certain termination conditions. This setting also affects the
operation when the distribution block is powered down with
0x230<1> = 1b (see the Distribution Power-Down section).
Individual Circuit Block Power-Down
Other AD9518 circuit blocks (such as CLK, REF1, and REF2)
can be powered down individually. This gives flexibility in
configuring the part for power savings whenever certain chip
functions are not needed.