OM11024 NXP Semiconductors, OM11024 Datasheet - Page 17

• Manufacturer Part Number: OM11024
• Description: KIT EVAL FOR LPC313X
• Manufacturer: NXP Semiconductors
• Type: Microcontrollerr

Specifications of OM11024

• Contents: 2 Boards, cable and software
• For Use With/related Products: LPC3131
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-4719

NXP Semiconductors
LPC3130_3131
Preliminary data sheet
6.6 External Bus Interface (EBI)
6.7 Internal ROM Memory
The EBI module acts as multiplexer with arbitration between the NAND flash and the
SDRAM/SRAM memory modules connected externally through the MPMC.
The main purpose for using the EBI module is to save external pins. However only data
and address pins are multiplexed. Control signals towards and from the external memory
devices are not multiplexed.
Table 7.
The internal ROM memory is used to store the boot code of the LPC3130/3131. After a
reset, the ARM processor will start its code execution from this memory.
The LPC3130/3131 ROM memory has the following features:
The boot ROM determines the boot mode based on reset state of GPIO0, GPIO1, and
GPIO2 pins. To ensure that GPIO0, GPIO1 and GPIO2 pins come up as inputs, pins
TRST_N and JTAGSEL must be LOW during power-on reset (see UM10314 JTAG
chapter for details).
LPC3130/3131:
Module
External SRAM0
External SRAM1
External SDRAM0 0x3000 0000
•
•
•
•
•
•
•
•
•
•
•
– extended wait
One chip select for synchronous memory and two chip selects for static memory
devices.
Power-saving modes.
Dynamic memory self-refresh mode supported.
Controller support for 2 k, 4 k, and 8 k row address synchronous memory parts.
Support for all AHB burst types.
Little and big-endian support.
Support for the External Bus Interface (EBI) that enables the memory controller pads
to be shared.
Supports booting from SPI flash, NAND flash, SD/SDHC/MMC cards, UART, and
USB (DFU class) interfaces.
Supports option to perform CRC32 checking on the boot image.
Supports booting from managed NAND devices such as moviNAND, iNAND,
eMMC-NAND and eSD-NAND using SD/MMC boot mode.
Contains pre-defined MMU table (16 kB) for simple systems.
Memory map of the external SRAM/SDRAM memory modules
All information provided in this document is subject to legal disclaimers.
Maximum address space
0x2000 0000
0x2000 0000
0x2002 0000
0x2002 0000
Table 8
Rev. 1.04 — 27 May 2010
shows the various boot modes supported on the
Low-cost, low-power ARM926EJ-S microcontrollers
0x2000 FFFF
0x2001 FFFF
0x2002 FFFF
0x2003 FFFF
0x37FF FFFF
Data width
8 bit
16 bit
8 bit
16 bit
16 bit
LPC3130/3131
© NXP B.V. 2010. All rights reserved.
64 kB
128 kB
64 kB
128 kB
128 MB
Device size
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