OM11024 NXP Semiconductors, OM11024 Datasheet - Page 23

• Manufacturer Part Number: OM11024
• Description: KIT EVAL FOR LPC313X
• Manufacturer: NXP Semiconductors
• Type: Microcontrollerr

Specifications of OM11024

• Contents: 2 Boards, cable and software
• For Use With/related Products: LPC3131
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-4719

NXP Semiconductors
LPC3130_3131
Preliminary data sheet
6.14 APB bridge
6.15 Clock Generation Unit (CGU)
The APB bridge is a bus bridge between the AMBA Advanced High-performance Bus
(AHB) and the ARM Peripheral Bus (APB) interface.
The module supports two different architectures:
The clock generation unit generates all clock signals in the system and controls the reset
signals for all modules. The structure of the CGU is shown in
generated by the CGU belongs to one of the domains. Each clock domain is fed by a
single base clock that originates from one of the available clock sources. Within a clock
domain, fractional dividers are available to divide the base clock to a lower frequency.
•
•
•
•
•
•
Supports all combinations of 32-bit masters and slaves (fully connected interconnect
matrix).
Round-robin priority mechanism for bus arbitration: all masters have the same priority
and get bus access in their natural order
Four devices on a master port (listed in their natural order for bus arbitration):
– DMA
– ARM926 instruction port
– ARM926 data port
– USB OTG
Devices on a slave port (some ports are shared between multiple devices):
– AHB to APB Bridge 0
– AHB to APB Bridge 1
– AHB to APB Bridge 2
– AHB to APB Bridge 3
– AHB to APB Bridge 4
– Interrupt Controller
– NAND flash controller
– MCI SD/SDIO
– USB 2.0 high-speed OTG
– 96 kB ISRAM
– 96 kB ISRAM (LPC3131 only)
– 128 kB ROM
– MPMC
Single-clock architecture, synchronous bridge. The same clock is used at the AHB
side and at the APB side of the bridge. The AHB-to-APB4 bridge uses this
architecture.
Dual-clock architecture, asynchronous bridge. Different clocks are used at the AHB
side and at the APB side of the bridge. The AHB-to-APB0, AHB-to-APB1,
AHB-to-APB2, and AHB-to-APB3 bridges use this architecture.
All information provided in this document is subject to legal disclaimers.
Rev. 1.04 — 27 May 2010
Low-cost, low-power ARM926EJ-S microcontrollers
LPC3130/3131
Figure
6. Each output clock
© NXP B.V. 2010. All rights reserved.
23 of 72