Z8018100ZCO Zilog, Z8018100ZCO Datasheet - Page 17

• Manufacturer Part Number: Z8018100ZCO
• Description: Z80181 SAC APPLICATION BOARD
• Manufacturer: Zilog

Specifications of Z8018100ZCO

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: Z8018100ZC0; Z8018100ZC0

Zilog
PROGRAMMING (Continued)
Address
00h
to 3Fh
E0h
E1h
E2h
E3h
E4h
E5h
E6h
E7h
E8h
E9h
EAh
EBh
ECh
EDh
EEh
EFh
DS971800500
Table 1. I/O Control Register Address
Z181 MPU Control Registers
(Relocatable to 040h-07Fh, or 080h-0BFh)
PIA1 Data Direction Register (P1DDR)
PIA1 Data Port (P1DP)
PIA2 Data Direction Register (P2DDR)
PIA2 Data Register (P2DP)
CTC Channel 0 Control Register (CTC0)
CTC Channel 1 Control Register (CTC1)
CTC Channel 2 Control Register (CTC2)
CTC Channel 3 Control Register (CTC3)
SCC Control Register (SCCCR)
SCC Data Register (SCCDR)
RAM Upper Boundary Address Register
(RAMUBR)
RAM Lower Boundary Address Register
(RAMLBR)
ROM Address Boundary Register (ROMBR)
System Configuration Register (SCR)
Reserved
Reserved
Register
PS009701-0301
Z181 MPU Control Registers
The I/O address for these registers can be relocated in 64
byte boundaries by programming of the I/O Control Reg-
ister (Address xx111111b).
Do not relocate these registers to address from 0C0h since
this will cause an overlap of the Z180 registers and the 16
registers of the Z181 (address 0E0h to 0EFh).
Also, the OMCR register (Address: xx111101b) must be
programmed as 0x0xxxxxb (x: don’t care) as a part of the
initialization procedure. The M1E bit (Bit D7) of this register
must be programmed as 0 or the interrupt daisy chain is
corrupted. The /IOC bit (Bit D5) of this register is pro-
grammed as 0 so that the timing of the /RD and /IORQ
signals are compatible with Z80 peripherals.
For detailed information, refer to the Z180 Technical Manual.
S
MART
A
CCESS
C
ONTROLLER
Z80181
2-17
SAC
™