Z8018100ZCO Zilog, Z8018100ZCO Datasheet - Page 54

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Z8018100ZCO

Manufacturer Part Number
Z8018100ZCO
Description
Z80181 SAC APPLICATION BOARD
Manufacturer
Zilog
Datasheet

Specifications of Z8018100ZCO

Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
Z8018100ZC0
Z8018100ZC0
Zilog
AC CHARACTERISTICS (Continued)
Z180 MPU Timing
2-54
(At edge
(At level
/DREQi
/DREQi
/TENDi
sense)
sence)
ST
Ø
DMA Control Signals
[1] tDRQS and tDRQH are specified for the rising edge of clock followed by T3.
[2] tDRQS and tDRQH are specified for the rising edge of clock.
[3] DMA cycle starts.
[4] CPU cycle starts.
T1
CPU or DMA Read/Write Cycle (Only DMA Write Cycle for /TENDi)
17
[3]
Figure 63. DMA Control Signals
PS009701-0301
46
T2
44
45
44
[2]
Tw
45
[1]
T3
S
MART
47
A
CCESS
T1
C
18
DS971800500
ONTROLLER
[4]
Z80181
SAC

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