Z8018100ZCO Zilog, Z8018100ZCO Datasheet - Page 45

• Manufacturer Part Number: Z8018100ZCO
• Description: Z80181 SAC APPLICATION BOARD
• Manufacturer: Zilog

Specifications of Z8018100ZCO

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: Z8018100ZC0; Z8018100ZC0

Zilog
System Configuration Register (I/O address EDh)
This register is to determine the functionality of PIA1 and
the Interrupt Daisy-Chain Configuration (Figure 13). This
register has the following control bits:
Bit D7. Reserved and should be programmed as “0”.
Bit D6. Daisy-Chain Configuration. Determines the
arrangement of the interrupt priority daisy chain.
When this bit is set to “1”, priority is as follows:
IEI pin - CTC - SCC - IEO pin
When this bit is “0”, priority is as follows:
IEI pin - SCC - CTC - IEO pin
This bit’s default (after Reset) is 0.
DS971800500
PS009701-0301
Bit D5. Disable /ROMCS. When this bit is set to “1”.
/ROMCS is forced to a “1” regardless of the status of the
address decode logic. This bit’s default (after Reset) is 0
and /ROMCS function is enabled.
Bit D4-D3. Reserved and should be programmed as “00”.
Bit D2. ROM Emulator Mode Enable. When this bit is set to
a 1, the Z181 is in “ROM emulator mode”. In this mode, bus
direction for certain transaction periods are set to the
opposite direction to export internal bus transactions out-
side the Z80181. This allows the use of ROM emulators/
logic analyzers for applications development. This bit’s
default (after Reset) is 0.
Bit D1. Reserved and shall be programmed as “0”.
Bit D0. CTC/PIA1. When this bit is set to “1”, PIA1 functions
as the CTC’s I/O pins. This bit’s default (after Reset) is 0.
S
MART
A
CCESS
C
ONTROLLER
Z80181
2-45
SAC
™