Z8018100ZCO Zilog, Z8018100ZCO Datasheet - Page 19

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Z8018100ZCO

Manufacturer Part Number
Z8018100ZCO
Description
Z80181 SAC APPLICATION BOARD
Manufacturer
Zilog
Datasheet

Specifications of Z8018100ZCO

Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
Z8018100ZC0
Z8018100ZC0
Zilog
General
Divide Ratio
SS, 2, 1, 0
000
001
010
011
100
101
110
111
DS971800500
Upon Reset
R/W
Bit
PS = 0
(Divide Ratio = 10)
DR = 0 (x16)
Ø
Ø
Ø
Ø
Ø
Ø
Ø
External Clock (Frequency < Ø
CNTLB0
Invalid
MPBT
R/W
† /CTS - Depending on the condition of /CTS pin.
160
320
640
1280
2560
5120
10240
PS - Cleared to 0.
R/W
MP
0
Figure 9. ASCI Control Register B (Ch. 0)
/CTS/
R/W
PS
PE0
R/W
0
DR = 1 (x64)
Ø
Ø
Ø
Ø
Ø
Ø
Ø
PS009701-0301
R/W
640
1280
2580
5120
10240
20480
40960
DR
0
40)
SS2
R/W
1
SS1
R/W
1
Addr 02h
PS = 1
(Divide Ratio = 30)
DR = 0 (x16)
Ø
Ø
Ø
Ø
Ø
Ø
Ø
SS0
R/W
1
480
960
1920
3840
7680
15360
30720
Clock Source and Speed Select
Divide Ratio
Parity Even or Odd
Clear To Send/Prescale
Multiprocessor
Multiprocessor Bit Transmit
S
MART
DR = 1 (x64)
Ø
Ø
Ø
Ø
Ø
Ø
Ø
A
1920
3840
7680
15360
30720
61440
122880
CCESS
C
ONTROLLER
Z80181
2-19
SAC

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