DSP56F803EVM Freescale Semiconductor, DSP56F803EVM Datasheet - Page 17

KIT EVALUATION FOR DSP56F803

DSP56F803EVM

Manufacturer Part Number
DSP56F803EVM
Description
KIT EVALUATION FOR DSP56F803
Manufacturer
Freescale Semiconductor

Specifications of DSP56F803EVM

Processor To Be Evaluated
56F803
Data Bus Width
16 bit
Interface Type
RS-232, JTAG
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Chapter 2
Technical Summary
The 56F803EVM is designed as a versatile controller development card for developing real-time
software and hardware products to support a new generation of applications in digital and
wireless messaging, servo and motor control, digital answering machines, feature phones,
modems, and digital cameras. The power of the 16-bit 56F803 controller, combined with the
on-board 64K 16-bit external program Static RAM (SRAM), 64K 16-bit external data
SRAM, CAN interface, Hall-Effect/Quadrature Encoder interface, motor zero crossing logic,
motor bus over-current logic, motor bus over-voltage logic and parallel JTAG interface, makes
the 56F803EVM ideal for developing and implementing many motor controlling algorithms, as
well as for learning the architecture and instruction set of the 56F803 processor.
The main features of the 56F803EVM include:
Freescale Semiconductor
• 56F803 16-bit +3.3V controller operating at 80MHz [U1]
• External fast Static RAM (FSRAM) memory [U2], configured as:
• 8.00MHz crystal oscillator for device frequency generation [Y1]
• Optional external oscillator frequency input connector [JG3 and JG9]
• Joint Test Action Group (JTAG) port interface connector for an external debug Host
• On-board Parallel JTAG Host Target Interface, with a connector for a PC printer port
• RS-232 interface for easy connection to a host processor [U3 and P4]
• CAN interface for high speed, 1.0Mbps, communications [U15 and J3]
• CAN bypass and bus termination [J13 and JG10]
• Connector to allow the user to connect his own SCI / GPIO-compatible peripheral [J12]
• Connector to allow the user to connect his own SPI / MPIO-compatible peripheral [J6]
• Connector to allow the user to connect his own PWM / GPIO-compatible peripheral [J4]
• Connector to allow the user to connect his own CAN physical layer peripheral [J5]
• Connector to allow the user to connect his own Timer / MPIO-compatible peripheral [J10]
— 64K 16-bit of Program memory with 0 wait states at 70MHz
— 64K 16-bit of Data memory with 0 wait states at 70MHz
Target Interface [J1]
cable [P2]
Technical Summary, Rev. 5
2-1

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