DSP56F803EVM Freescale Semiconductor, DSP56F803EVM Datasheet - Page 22

KIT EVALUATION FOR DSP56F803

DSP56F803EVM

Manufacturer Part Number
DSP56F803EVM
Description
KIT EVALUATION FOR DSP56F803
Manufacturer
Freescale Semiconductor

Specifications of DSP56F803EVM

Processor To Be Evaluated
56F803
Data Bus Width
16 bit
Interface Type
RS-232, JTAG
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
2.4 Clock Source
The 56F803EVM uses an 8.00MHz crystal, Y1, connected to its External Crystal Inputs, EXTAL
and XTAL. The 56F803 uses its internal PLL to multiply the input frequency by 10 to achieve its
80MHz maximum operating frequency. An external oscillator source can be connected to the
controller by using the oscillator bypass connectors, JG3 and JG9; see
2.5 Operating Mode
The 56F803EVM provides a boot-up MODE selection jumper, JG4. This jumper is used to select
the operating mode of the controller as it exits RESET. Refer to the DSP56F801-7 User’s Manual
for a complete description of the chip’s operating modes.
modes available on the 56F803.
2-6
Operating Mode
Figure 2-3. Schematic Diagram of the Clock Interface
0
3
OSCILLATOR
8.00MHz
EXTERNAL
Table 2-2. Operating Mode Selection
HEADERS
DSP56F803EVM User Manual, Rev. 5
No Jumper
JG4
1–2
JG3
JG9
Bootstrap from internal memory (GND)
Bootstrap from external memory (+3.3V)
Table 2-2
EXTAL
XTAL
Comment
56F803
shows the two operation
Figure
Freescale Semiconductor
2-3.

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