HS7760KCM02H Renesas Electronics America, HS7760KCM02H Datasheet - Page 227

• Manufacturer Part Number: HS7760KCM02H
• Description: ON CHIP DEBUG EMULATOR W/TRACE
• Manufacturer: Renesas Electronics America

Specifications of HS7760KCM02H

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

The SH7760 E10A emulator has sequential break functions. Table 6.6 lists the sequential break
conditions.
Table 6.6 Sequential Break Conditions
No.
1
2
3
4
Note: Sequential breaks can be specified by the [Configuration] dialog box.
Notes on Setting the [Break Condition] Dialog Box and BREAKCONDITION_SET
Command:
1. When [Go to cursor], [Step In], [Step Over], or [Step Out] is selected, the settings of Break
2. Break Condition 3 is disabled when an instruction to which a BREAKPOINT has been set is
3. When a Break Condition is satisfied, emulation may stop after two or more instructions have
4. If a PC break before execution is set to the slot instruction after a delayed branch instruction,
5. Break Condition 6,7 uses the UBC. When the UBC is used in the user program, change the
user program execution cannot be terminated before the slot instruction execution; execution
stops before the branch destination instruction.
UBC setting for users by using the [UBC_mode] list box in the [Configuration] dialog box or
the UBC_mode command.
Condition 3 are disabled.
executed. Accordingly, do not set a BREAKPOINT to an instruction which satisfies Break
Condition 3.
been executed.
Break Condition
Sequential break condition 2-1
Sequential break condition 3-2-1
Sequential break condition 4-3-2-1
Sequential break condition 7-6
Numbers 1 to 3 in table 6.6 can be set in the [Emulation_mode] list box in the
[Configuration] dialog box or with the Go_option command. For details on command-line
syntax, refer to the online help function.
Number 4 can be set in the [UBC_mode] list box in the [Configuration] dialog box or with
the UBC_mode command. For details on command-line syntax, refer to the online help
function.
Description
Program is halted when Break Condition 2 and
Break Condition 1 are satisfied in that order. Break
Condition 2,1 should be set.
Program is halted when Break Condition 3, Break
Condition 2, and Break Condition 1 are satisfied in
that order. Break Condition 3,2,1 should be set.
Program is halted when Break Condition 4, Break
Condition 3, Break Condition 2, and Break Condition
1 are satisfied in that order. Break Condition 4,3,2,1
should be set.
Program is halted when Break Condition 7 and
Break Condition 6 are satisfied in that order. Break
Condition 7,6 should be set.
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