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Spartan-3E FPGA Starter Kit Board User Guide UG230 (v1.2) January 20, 2011 R ...
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Xilinx is disclosing this Document and Intellectual Property (hereinafter “the Design”) to you for use in the development of designs to operate on, or interface with Xilinx FPGAs. Except as stated herein, none of the Design may be copied, reproduced, ...
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Table of Contents Preface: About This Guide Acknowledgements Guide Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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SMA Clock Input or Output Connector UCF Constraints Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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R Writing Data to the Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Related Resources Chapter 11: Intel StrataFlash Parallel NOR Flash PROM StrataFlash Connections Shared Connections Character LCD . . . . . . . . . . . . . . . . . . . . . . . . ...
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R UCF Location Constraints Related Resources Chapter 15: Expansion Connectors Hirose 100-pin FX2 Edge Connector (J3) Voltage Supplies to the Connector . . . . . . . . . . . . . . . . . . . ...
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DDR SDRAM Series Termination and FX2 Connector Differential Termination Appendix B: Example User Constraints File (UCF) 8 www.xilinx.com Spartan-3E FPGA Starter Kit Board User Guide UG230 (v1.2) January 20, 2011 R 158 ...
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R About This Guide This user guide provides basic information on the Spartan-3E FPGA Starter Kit board capabilities, functions, and design. It includes general information on how to use the various peripheral functions included on the board. For detailed reference ...
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Preface: About This Guide • Chapter 5, “Character LCD Screen,” screen. • Chapter 6, “VGA Display Port,” • Chapter 7, “RS-232 Serial Ports,” • Chapter 8, “PS/2 Mouse/Keyboard Port,” mouse and keyboard port. • Chapter 9, “Digital to Analog Converter ...
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R Introduction and Overview Thank you for purchasing the Xilinx Spartan in developing your Spartan-3E FPGA application. Choose the Starter Kit Board for Your Needs Depending on specific requirements, choose the Xilinx development board that best suits your needs. Spartan-3E ...
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Chapter 1: Introduction and Overview Key Components and Features The key features of the Spartan-3E Starter Kit board are: • Xilinx XC3S500E Spartan-3E FPGA • 232 user-I/O pins • 320-pin FBGA package • Over 10,000 logic cells • ...
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R Design Trade-Offs A few system-level design trade-offs were required in order to provide the Spartan-3E Starter Kit board with the most functionality. Configuration Methods Galore! A typical FPGA application uses a single non-volatile memory to store configuration images. To ...
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Chapter 1: Introduction and Overview 14 www.xilinx.com Spartan-3E FPGA Starter Kit Board User Guide UG230 (v1.2) January 20, 2011 R ...
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R Switches, Buttons, and Knob Slide Switches Locations and Labels The Spartan The slide switches are located in the lower right corner of the board and are labeled SW3 through SW0. Switch SW3 is the left-most switch, and SW0 is ...
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Chapter 2: Switches, Buttons, and Knob NET "SW<0>" NET "SW<1>" NET "SW<2>" NET "SW<3>" Push-Button Switches Locations and Labels The Spartan-3E FPGA Starter Kit board has four momentary-contact push-button switches, shown in board and are labeled BTN_NORTH, BTN_EAST, BTN_SOUTH, and ...
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R Figure 2-4: Push-Button Switches Require an Internal Pull-Down Resistor in FPGA In some applications, the BTN_SOUTH push-button switch is also a soft reset that selectively resets functions within the FPGA. UCF Location Constraints Figure 2-5 I/O pin assignment and ...
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Chapter 2: Switches, Buttons, and Knob 3.3V Figure 2-6: Push-Button Switches Require Internal Pull-up Resistor in FPGA Input Rotary Shaft Encoder In principal, the rotary shaft encoder behaves much like a cam, connected to central shaft. Rotating the shaft then ...
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R direction! See the Rotary Encoder Interface reference design example. Rising edge on ‘A’ when ‘B’ is Low indicates RIGHT (clockwise) rotation Rotating RIGHT A B Figure 2-8: Outputs from Rotary Shaft Encoder May Include Mechanical Chatter UCF Location Constraints ...
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Chapter 2: Switches, Buttons, and Knob Operation Each LED has one side connected to ground and the other side connected to a pin on the Spartan-3E device via a 390Ω current limiting resistor. To light an individual LED, drive the ...
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R Clock Sources Overview As shown in clock input sources, all of which are located below the Xilinx logo, near the Spartan-3E logo. • The board includes an on-board 50 MHz clock oscillator. • Clocks can be supplied off-board via ...
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Chapter 3: Clock Sources Clock Connections Each of the clock inputs connect directly to a global buffer input in I/O Bank 0, along the top of the FPGA. As shown in an associated DCM. Table 3-1: Clock Inputs and Associated ...
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R NET "CLK_50MHZ" NET "CLK_SMA" NET "CLK_AUX" Clock Period Constraints The Xilinx ISE Set the clock PERIOD constraint as appropriate. An example constraint appears in Figure 3-3 50 MHz, which equates period. The output duty cycle ...
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Chapter 3: Clock Sources 24 www.xilinx.com Spartan-3E FPGA Starter Kit Board User Guide UG230 (v1.2) January 20, 2011 R ...
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R FPGA Configuration Options The Spartan options: • Download FPGA designs directly to the Spartan-3E FPGA via JTAG, using the on- board USB interface. The on-board USB-JTAG logic also provides in-system programming for the on-board Platform Flash PROM and the ...
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Chapter 4: FPGA Configuration Options 16 Mbit ST Micro SPI Serial Flash Serial Peripheral Interface (SPI) mode USB-based Download/Debug Port Uses standard USB cable Figure 4-1: Spartan-3E Starter Kit FPGA Configuration Options Configuration Mode Jumper Settings (Header J30) Select between ...
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R The configuration mode jumpers determine which configuration mode the FPGA uses when power is first applied, or whenever the PROG button is pressed. The DONE pin LED lights when the FPGA successfully finishes configuration. Pressing the PROG button forces ...
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Chapter 4: FPGA Configuration Options Table 4-1: Spartan-3E Configuration Mode Jumper Settings (Header J30 in Figure 4-2) Configuration Mode BPI Down (see Chapter 11, “Intel StrataFlash Parallel NOR Flash PROM”) JTAG PROG Push Button The PROG push button, shown in ...
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R Programming the FPGA, CPLD, or Platform Flash PROM via USB As shown in programming logic and an USB endpoint with a Type B connector. Via a USB cable connection with the host PC, the iMPACT programming software directly programs ...
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Chapter 4: FPGA Configuration Options Programming via iMPACT After successfully compiling an FPGA design using the Xilinx development software, the design can be downloaded using the iMPACT programming software and the USB cable. To begin programming, connect the USB cable ...
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R If the original FPGA configuration file used the default StartUp clock source, CCLK, iMPACT issues the warning message shown in ignored. When downloading via JTAG, the iMPACT software must change the StartUP clock source to use the TCK JTAG ...
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Chapter 4: FPGA Configuration Options Figure 4-9: iMPACT Programming Succeeded, the FPGA’s DONE Pin is High Programming Platform Flash PROM via USB The on-board USB-JTAG circuitry also programs the Xilinx XCF04S serial Platform Flash PROM. The steps provided in this ...
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R Click Configuration Options as shown in Rate drop list, choose 25 to increase the internal CCLK oscillator to approximately 25 MHz, the fastest frequency when using an XCF04S Platform Flash PROM. Click OK when finished. Figure 4-11: Set CCLK ...
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Chapter 4: FPGA Configuration Options To regenerate the programming file, double-click Generate Programming File, as shown in Figure Generating the PROM File After generating the program file, double-click Generate PROM, ACE, or JTAG File to launch the iMPACT software, as ...
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R Choose Xilinx PROM as the target PROM type, as shown in of the PROM File Formats; the Intel Hex format (MCS) is popular. Enter the Location of the directory and the PROM File Name. Click Next > when finished. ...
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Chapter 4: FPGA Configuration Options The Spartan-3E Starter Kit board has an XCF04S Platform Flash PROM. Select xcf04s from the drop list, as shown in The PROM Formatter then echoes the settings, as shown in Figure 4-17: Click Finish after ...
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R When PROM formatting is complete, the iMPACT software presents the present settings by showing the PROM, the select FPGA bitstream(s), and the amount of PROM space consumed by the bitstream. bitstream stored in an XCF04S Platform Flash PROM. Spartan-3E ...
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Chapter 4: FPGA Configuration Options To generate the actual PROM file, click Operations Generate File as shown in Figure 4-20. Figure 4-20: Click Operations Generate File to Create the Formatted PROM File The iMPACT software indicates that the ...
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R Assign the PROM file to the XCF04S Platform Flash PROM on the JTAG chain, as shown in Figure 4-23. Right-click the PROM icon, then click Assign New Configuration File. Select a previously generated PROM format file and click OK. ...
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Chapter 4: FPGA Configuration Options The programming software again prompts for the PROM type to be programmed. Select xcf04s and click OK, as shown in Before programming, choose the programming options available in the Erase Before Programming option erases the ...
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R The iMPACT software indicates if programming was successful or not. If programming was successful and the Load FPGA option was left unchecked, push the PROG_B push- button switch shown in newly programmed Platform Flash PROM. If the FPGA successfully ...
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Chapter 4: FPGA Configuration Options 42 www.xilinx.com Spartan-3E FPGA Starter Kit Board User Guide UG230 (v1.2) January 20, 2011 R ...
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R Character LCD Screen Overview The Spartan liquid crystal display (LCD). The FPGA controls the LCD via the 4-bit data interface shown in Figure 5-1. Although the LCD supports an 8-bit data interface, the Starter Kit board uses a 4-bit ...
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Chapter 5: Character LCD Screen Character LCD Interface Signals Table 5-1 shows the interface character LCD interface signals. Table 5-1: Character LCD Interface Signal Name SF_D<11> SF_D<10> SF_D<9> SF_D<8> LCD_E LCD_RS LCD_RW Voltage Compatibility The character LCD is power by ...
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R If the StrataFlash memory is in byte-wide (x8) mode (SF_BYTE = Low), the FPGA application has full simultaneous read/write access to both the LCD and the StrataFlash memory. In byte-wide mode, the StrataFlash memory does not use the SF_D<15:8> ...
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Chapter 5: Character LCD Screen Physically, there are 80 total character locations in DD RAM with 40 characters available per line. Locations 0x10 through 0x27 and 0x50 through 0x67 can be used to store other non-display data. Alternatively, these locations ...
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R The character ROM contains the ASCII English character set and Japanese kana characters. The controller also provides for eight custom character bitmaps, stored in eight custom characters are displayed by storing character codes 0x00 through 0x07 ...
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Chapter 5: Character LCD Screen The CG RAM address counter can either remain constant after read or write operations, or auto-increments or auto-decrements by one location, as defined by the I/D set by the Mode Set Figure 5-5 character is ...
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R Table 5-3: LCD Character Display Command Set (Continued) Function Function Set Set CG RAM Address Set DD RAM Address Read Busy Flag and Address Write Data to CG RAM or DD RAM Read Data from CG RAM or DD ...
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Chapter 5: Character LCD Screen This bit either auto-increments or auto-decrements the DD RAM and CG RAM address counter by one location after each CG RAM or DD RAM Bit DB0: (S) Shift 0 Shifting disabled 1 During a DD ...
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R Table 5-4: Shift Patterns According to S/C and R/L Bits DB3 DB2 (S/C) (R/ Function Set Sets interface data length, number of display lines, and character font. The Starter Kit board ...
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Chapter 5: Character LCD Screen After the write operation, the address is automatically incremented or decremented by 1 according to the Execution Time: 40 μs Read Data from CG RAM or DD RAM Read data from DD RAM if the ...
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R The data values on SF_D<11:8>, and the register select (LCD_RS) and the read/write (LCD_RW) control signals must be set up and stable at least 40 ns before the enable LCD_E goes High. The enable signal must remain High for ...
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Chapter 5: Character LCD Screen • Finally, issue a after issuing this command. Writing Data to the Display To write data to the display, specify the start address, followed by one or more data values. Before writing any data, issue ...
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R VGA Display Port The Spartan connector. Connect this port directly to most PC monitors or flat-panel LCDs using a standard monitor cable. As shown in connector along the top of the board. Pin 5 Pin 10 Pin 15 DB15 ...
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Chapter 6: VGA Display Port Table 6-1: 3-Bit Display Color Codes VGA_RED VGA signal timing is specified, published, copyrighted, and sold by the Video Electronics Standards Association (VESA). The following VGA system ...
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R pixel 0,0 Current pixel 479,0 through the horizontal deflection coil Stable current ramp: Information is displayed during this time time "front porch" HS Figure 6-2: CRT Display Timing Example The display resolution defines the size of the beams, the ...
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Chapter 6: VGA Display Port As shown in sync (VS) timings signals and coordinates the delivery of video data on each pixel clock. The pixel clock defines the time available to display one pixel of information. The VS signal defines ...
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R UCF Location Constraints Figure 6-4 assignment, the I/O standard used, the output slew rate, and the output drive current. NET "VGA_RED" NET "VGA_GREEN" NET "VGA_BLUE" NET "VGA_HSYNC" NET "VGA_VSYNC" Related Resources • VESA http://www.vesa.org • VGA timing information http://www.epanorama.net/documents/pc/vga_timing.html ...
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Chapter 6: VGA Display Port 60 www.xilinx.com Spartan-3E FPGA Starter Kit Board User Guide UG230 (v1.2) January 20, 2011 R ...
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R RS-232 Serial Ports Overview As shown in ports: a female DB9 DCE connector and a male DTE connector. The DCE-style port connects directly to the serial port connector available on most personal computers and workstations via a standard straight-through ...
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Chapter 7: RS-232 Serial Ports Figure 7-1 FPGA supplies serial output data using LVTTL or LVCMOS levels to the Maxim device, which in turn, converts the logic value to the appropriate RS-232 voltage level. Likewise, the Maxim device converts the ...
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R PS/2 Mouse/Keyboard Port The Spartan standard 6-pin mini-DIN connector, labeled J14 on the board. connector, and connector attach to the FPGA. Table 8-1: PS/2 Connector Pinout PS/2 DIN Pin Both a PC mouse ...
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Chapter 8: PS/2 Mouse/Keyboard Port organized differently for a mouse and keyboard. Furthermore, the keyboard interface allows bidirectional data transfers so the host device can illuminate state LEDs on the keyboard. The PS/2 bus timing appears in only driven when ...
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R ESC Caps Lock 58 ...
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Chapter 8: PS/2 Mouse/Keyboard Port Mouse A mouse generates a clock and data signal when moved; otherwise, these signals remain High, indicating the Idle state. Each time the mouse is moved, the mouse sends three 11-bit words to the host. ...
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R Voltage Supply The PS/2 port on the Spartan-3E FPGA Starter Kit board is powered by 5V. Although the Spartan-3E FPGA is not a 5V-tolerant device, it can communicate with a 5V device using series current-limiting resistors, as shown in ...
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Chapter 8: PS/2 Mouse/Keyboard Port 68 www.xilinx.com Spartan-3E FPGA Starter Kit Board User Guide UG230 (v1.2) January 20, 2011 R ...
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R Digital to Analog Converter (DAC) The Spartan Digital-to-Analog Converter (DAC). The DAC device is a Linear Technology LTC2624 quad DAC with 12-bit unsigned resolution. The four outputs from the DAC appear on the J5 header, which uses the Digilent ...
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Chapter 9: Digital to Analog Converter (DAC) Spartan-3E FPGA (N10) Interface Signals Table 9-1 lists the interface signals between the FPGA and the DAC. The SPI_MOSI, SPI_MISO, and SPI_SCK signals are shared with other devices on the SPI bus. The ...
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R Table 9-2: Disabled Devices on the SPI Bus Signal SPI_SS_B AMP_CS AD_CONV SF_CE0 FPGA_INIT_B SPI Communication Details Figure 9-3 received relative to the SPI_SCK clock signal. The bus is fully static and supports clocks rate up to the maximum ...
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Chapter 9: Digital to Analog Converter (DAC) SPI_MISO 0 SPI_MOSI x x DAC_CS Master Spartan-3E SPI_SCK Don’t Care FPGA Figure 9-4: SPI Communications Protocol to LTC2624 DAC The FPGA first sends eight dummy or “don’t care” bits, followed by a ...
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R UCF Location Constraints Figure 9-5 assignment and the I/O standard used. NET "SPI_MISO" NET "SPI_MOSI" NET "SPI_SCK" NET "DAC_CS" NET "DAC_CLR" Related Resources • LTC2624 Quad DAC Data Sheet http://www.linear.com/pc/downloadDocument.do?navId=H0,C1,C1155,C1005,C1156,P2048,D2170 • PicoBlaze Based D/A Converter Control for the Spartan-3E ...
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Chapter 9: Digital to Analog Converter (DAC) 74 www.xilinx.com Spartan-3E FPGA Starter Kit Board User Guide UG230 (v1.2) January 20, 2011 R ...
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R Analog Capture Circuit The Spartan consisting of a programmable scaling pre-amplifier and an analog-to-digital converter (ADC), as shown in 6-pin ADC Header (J7) The analog capture circuit consists of a Linear Technology LTC6912-1 programmable pre- amplifier that scales the ...
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Chapter 10: Analog Capture Circuit Header J7 REFAB (3.3V) REFCD (2.5V) VINA VINB GND VCC (3.3V) REF = 1.65V Spartan-3E FPGA SPI_MOSI (N10) (T4) (E18) (N7) AMP_CS (U16) SPI_SCK AMP_SHDN (P7) AD_CONV (P11) AMP_DOUT SPI_MISO Figure 10-2: Detailed View of ...
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R Finally, the ADC presents a 14-bit, two’s complement digital output. A 14-bit, two’s complement number represents values between -2 scaled by 8192 See “Programmable Pre-Amplifier” pre-amplifier. The reference design files provide more information on converting the voltage ...
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Chapter 10: Analog Capture Circuit Table 10-2: Programmable Gain Settings for Pre-Amplifier (Continued) Gain -5 -10 -20 -50 -100 SPI Control Interface Figure 10-3 for each amplifier is sent as an 8-bit command word, consisting of two 4-bit fields. The ...
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R The amplifier interface is relatively slow, supporting only about a 10 MHz clock frequency. UCF Location Constraints Figure 10-5 including the I/O pin assignment and I/O standard used. NET "SPI_MOSI" NET "AMP_CS" NET "SPI_SCK" NET "AMP_SHDN" NET "AMP_DOUT" Analog ...
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Chapter 10: Analog Capture Circuit SPI_MISO AD_CONV Spartan-3E Z FPGA SPI_SCK Master Converted data is presented with a latency of one sample. The sampled analog value is converted to digital data 32 SPI_SCK ...
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R Disable Other Devices on the SPI Bus to Avoid Contention The SPI bus signals are shared by other devices on the board vital that other devices are disabled when the FPGA communicates with the AMP or ADC ...
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Chapter 10: Analog Capture Circuit 82 www.xilinx.com Spartan-3E FPGA Starter Kit Board User Guide UG230 (v1.2) January 20, 2011 R ...
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R Intel StrataFlash Parallel NOR Flash PROM As shown in Mbyte) Intel StrataFlash parallel NOR Flash PROM. As indicated, some of the StrataFlash connections are shared with other components on the board. Spartan-3E FPGA CoolRunner-II CPLD The StrataFlash PROM provides ...
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Chapter 11: Intel StrataFlash Parallel NOR Flash PROM • Stores MicroBlaze processor code in the StrataFlash device and shadows the code into the DDR memory before executing the code. • Stores non-volatile data from the FPGA. StrataFlash Connections Table 11-1 ...
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R Table 11-1: FPGA-to-StrataFlash Connections Category Spartan-3E FPGA Starter Kit Board User Guide UG230 (v1.2) January 20, 2011 StrataFlash FPGA Pin Signal Name Number SF_A24 A11 Shared with XC2C64A CPLD. The CPLD actively drives these pins during FPGA SF_A23 N11 ...
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Chapter 11: Intel StrataFlash Parallel NOR Flash PROM Table 11-1: FPGA-to-StrataFlash Connections Category 86 StrataFlash FPGA Pin Signal Name Number SF_D15 T8 Upper 8 bits of a 16-bit halfword when SF_D14 R8 StrataFlash is SF_D13 P6 configured for x16 data ...
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R Shared Connections Besides the connections to the FPGA, the StrataFlash memory shares some connections to other components. Character LCD The character LCD uses a four-bit data interface. The display data connections are also shared with the SF_D<11:8> signals on ...
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Chapter 11: Intel StrataFlash Parallel NOR Flash PROM UCF Location Constraints Address Figure 11-2 I/O pin assignment and the I/O standard used. NET "SF_A<24>" NET "SF_A<23>" NET "SF_A<22>" NET "SF_A<21>" NET "SF_A<20>" NET "SF_A<19>" NET "SF_A<18>" NET "SF_A<17>" NET "SF_A<16>" ...
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R Control Figure 11-4 I/O pin assignment and the I/O standard used. NET "SF_BYTE" NET "SF_CE0" NET "SF_OE" NET "SF_STS" NET "SF_WE" Figure 11-4: UCF Location Constraints for StrataFlash Control Pins Setting the FPGA Mode Select Pins Set the FPGA ...
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Chapter 11: Intel StrataFlash Parallel NOR Flash PROM 90 www.xilinx.com Spartan-3E FPGA Starter Kit Board User Guide UG230 (v1.2) January 20, 2011 R ...
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R SPI Serial Flash The Spartan SPI serial Flash, useful in a variety of applications. The SPI Flash provides an alternative means to configure the FPGA—a new feature of Spartan-3E FPGAs as shown in Figure 12-1. The SPI Flash is ...
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Chapter 12: SPI Serial Flash Configuring from SPI Flash To configure the FPGA from SPI Flash, the FPGA mode select pins must be set appropriately and the SPI Flash must contain a valid configuration image. Select SPI Mode using Jumper ...
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R Creating an SPI Serial Flash PROM File The following steps describe how to format an FPGA bitstream for an SPI Serial Flash PROM. Setting the Configuration Clock Rate The FPGA supports a 12 MHz configuration clock rate when connected ...
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Chapter 12: SPI Serial Flash Formatting an SPI Flash PROM File After generating the program file, double-click Generate PROM, ACE, or JTAG File to launch the iMPACT software, as shown in After iMPACT starts, double-click PROM File Formatter, as shown ...
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R Figure 12-8: Choose the PROM Target Type, the, Data Format, and File Location The Spartan-3E Starter Kit board has a 16 Mbit SPI serial Flash PROM. Select 16M from the drop list, as shown in The PROM Formatter then ...
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Chapter 12: SPI Serial Flash Figure 12-10: Click Finish after Entering PROM Formatter Settings The PROM Formatter then prompts for the name(s) of the FPGA configuration bitstream file. As shown in (*.bit). Choose No after selecting the last FPGA file. ...
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R To generate the actual PROM file, click Operations Generate File as shown in Figure 12-13. Figure 12-13: Click Operations Generate File to Create the Formatted PROM File As shown in successfully created. The PROM Formatter creates an ...
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Chapter 12: SPI Serial Flash • Via the FPGA’s JTAG chain, use a JTAG tool to program the SPI Flash connected to the FPGA. See the link to the Universal Scan SPI Flash programming tutorial in Resources,” page Downloading the ...
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R a) JTAG3 Parallel Connector Figure 12-15: Attaching a JTAG Parallel Programming Cable to the Board Table 12-2: Cable Connections to J12 Header Cable and Labels J12 Header Label JTAG3 Cable Label Flying Leads Label Insert Jumper on JP8 and ...
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Chapter 12: SPI Serial Flash After programming the SPI Flash, remove jumper JP8, as shown in properly programmed, the FPGA then configures itself from the SPI Flash PROM and the DONE LED lights. The DONE LED is shown in Additional ...
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R Table 12-3: Disable Other Devices on SPI Bus Signal DAC_CS AMP_CS AD_CONV SF_CE0 FPGA_INIT_B Other SPI Flash Control Signals The M25P16 SPI Flash has two additional control inputs. The active-Low write protect input (W) and the active-Low bus hold ...
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Chapter 12: SPI Serial Flash be left floating. Why support multiple packages word, flexibility. The multi-package layout provides ... • Density migration between smaller- and larger-density SPI Flash PROMs. Not all SPI Flash densities are available in all ...
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R Related Resources • Xilinx Parallel Cable IV • Digilent JTAG3 Programming Cable http://www.digilentinc.com/Products/Catalog.cfm?NavPath=2,395&Cat=5#JTAG3 • STMicroelectronics M25P16 SPI Serial Flash Data Sheet http://www.numonyx.com/Documents/Datasheets/M25P16.pdf • PicoBlaze SPI Serial Flash Programmer, via RS-232 (Reference Design) http://www.xilinx.com/s3estarter • Using Serial Flash on the ...
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Chapter 12: SPI Serial Flash 104 www.xilinx.com Spartan-3E FPGA Starter Kit Board User Guide UG230 (v1.2) January 20, 2011 R ...
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R DDR SDRAM The Spartan Technology DDR SDRAM (MT46V32M16) with a 16-bit data interface, as shown in Figure 13-1. All DDR SDRAM interface pins connect to the FPGA’s I/O Bank 3 on the FPGA. I/O Bank 3 and the DDR ...
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Chapter 13: DDR SDRAM All DDR SDRAM interface signals are terminated. The differential clock pin SD_CK_P is fed back into FPGA pin B9 in I/O Bank 0 to have best access to one of the FPGA’s Digital Clock Managers (DCMs). ...
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R Table 13-1: FPGA-to-DDR SDRAM Connections (Continued) Category Spartan-3E FPGA Starter Kit Board User Guide UG230 (v1.2) January 20, 2011 DDR SDRAM FPGA Pin Signal Name Number SD_DQ15 H5 Data input/output SD_DQ14 H6 SD_DQ13 G5 SD_DQ12 G6 SD_DQ11 F2 SD_DQ10 ...
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Chapter 13: DDR SDRAM UCF Location Constraints Address Figure 13-2 address pins, including the I/O pin assignment and the I/O standard used. NET "SD_A<12>" NET "SD_A<11>" NET "SD_A<10>" NET "SD_A<9>" NET "SD_A<8>" NET "SD_A<7>" NET "SD_A<6>" NET "SD_A<5>" NET "SD_A<4>" ...
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R Control Figure 13-4 control pins, including the I/O pin assignment and the I/O standard used. NET "SD_BA<0>" NET "SD_BA<1>" NET "SD_CAS" NET "SD_CK_N" NET "SD_CK_P" NET "SD_CKE" NET "SD_CS" NET "SD_LDM" NET "SD_LDQS" NET "SD_RAS" NET "SD_UDM" NET "SD_UDQS" ...
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Chapter 13: DDR SDRAM 110 www.xilinx.com Spartan-3E FPGA Starter Kit Board User Guide UG230 (v1.2) January 20, 2011 R ...
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R 10/100 Ethernet Physical Layer Interface The Spartan 10/100 Ethernet physical layer (PHY) interface and an RJ-45 connector, as shown in Figure 14-1. With an Ethernet Media Access Controller (MAC) implemented in the FPGA, the board can optionally connect to ...
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Chapter 14: 10/100 Ethernet Physical Layer Interface Ethernet PHY Connections The FPGA connects to the LAN83C185 Ethernet PHY using a standard Media Independent Interface (MII), as shown in signals, including the FPGA pin number, appears in Spartan-3E FPGA Table 14-1: ...
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R Table 14-1: FPGA Connections to the LAN83C185 Ethernet PHY (Continued) Signal Name E_RX_CLK E_CRS E_COL E_MDC E_MDIO MicroBlaze Ethernet IP Cores The Ethernet PHY is primarily intended for use with MicroBlaze applications. As such, an Ethernet MAC is part ...
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Chapter 14: 10/100 Ethernet Physical Layer Interface The hardware evaluation versions of the Ethernet MAC cores operate for approximately eight hours in silicon before timing out. To order the full version of the core, visit the Xilinx website at: http://www.xilinx.com/products/ipcenter/OPB_10_100_Lite.htm ...
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R Expansion Connectors The Spartan easy interface flexibility to other off-board components. The board includes the following I/O expansion headers (see • A Hirose 100-pin edge connector with 43 associated FPGA user-I/O pins, including differential LVDS I/O ...
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Chapter 15: Expansion Connectors Figure 15-2: FPGA Connections to the Hirose 100-pin Edge Connector Three signals are reserved primarily as clock signals between the board and FX2 connector, although all three connect to full I/O pins. Voltage Supplies to the ...
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R Table 15-1: Hirose 100-pin FX2 Connector Pinout and FPGA Connections (J3) Shared Header Connections Signal Name FPGA Pin VCCO_0 VCCO_0 TMS_B JTSEL TDO_FX2 FX2_IO1 B4 FX2_IO2 A4 FX2_IO3 D5 FX2_IO4 C5 FX2_IO5 A6 FX2_IO6 B6 FX2_IO7 E7 FX2_IO8 F7 ...
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Chapter 15: Expansion Connectors Table 15-1: Hirose 100-pin FX2 Connector Pinout and FPGA Connections (J3) (Continued) Shared Header Connections Signal Name FPGA Pin FX2_IO30 C4 FX2_IO31 B11 FX2_IO32 A11 FX2_IO33 A8 FX2_IO34 G9 FX2_IP35 D12 FX2_IP36 C12 FX2_IP37 A15 FX2_IP38 ...
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R Table 15-2: Differential I/O Pairs Differential Pair Signal Name FX2_IO1 1 FX2_IO2 FX2_IO3 2 FX2_IO4 FX2_IO5 3 FX2_IO6 FX2_IO7 4 FX2_IO8 FX2_IO9 5 FX2_IO10 FX2_IO11 6 FX2_IO12 FX2_IO13 7 FX2_IO14 FX2_IO15 8 FX2_IO16 FX2_IO17 9 FX2_IO18 FX2_IO19 10 FX2_IO20 ...
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Chapter 15: Expansion Connectors Using Differential Inputs LVDS and RSDS differential inputs require input termination. Two options are available. The first option is to use external termination resistors, as shown in board provides landing pads for external 100Ω termination resistors. ...
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R Figure 15-5: Location of Termination Resistor Pads on Bottom Side of Board Using Differential Outputs Differential input signals do not require any special voltage. LVDS and RSDS differential outputs signals, on the other hand, require a 2.5V supply on ...
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Chapter 15: Expansion Connectors # ==== FX2 Connector (FX2) ==== NET "FX2_CLKIN" NET "FX2_CLKIO" NET "FX2_CLKOUT" # These four connections are shared with the J1 6-pin accessory header NET "FX2_IO<1>" NET "FX2_IO<2>" NET "FX2_IO<3>" NET "FX2_IO<4>" # These four connections ...
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R Six-Pin Accessory Headers The 6-pin accessory headers provide easy I/O interface expansion using the various Digilent Peripheral Modules (see headers is provided in Header J1 The J1 header, shown in the board. It uses a female 6-pin 90° socket. ...
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Chapter 15: Expansion Connectors Header J4 The J4 header, shown in uses a 6-pin header consisting of 0.1-inch centered stake pins. Four FPGA pins connect to the J4 header, FX2_IO<12:9>. These four signals are also shared with the Hirose FX2 ...
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R Connectorless Debugging Port Landing Pads (J6) Landing pads for a connectorless debugging port are provided as header J6, shown in Figure 15-1, page probe, such as those available from Agilent, provides an interface to a logic analyzer. This debugging ...
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Chapter 15: Expansion Connectors Related Resources • Hirose connectors http://www.hirose-connectors.com/ • FX2 Series Connector Data Sheet http://www.hirose.co.jp/cataloge_hp/e57220088.pdf • Digilent, Inc. Peripheral Modules http://www.digilentinc.com/Products/Catalog.cfm?NavPath=2,401&Cat=9 • Xilinx ChipScope Pro Tool http://www.xilinx.com/tools/cspro.htm • Agilent B4655A FPGA Dynamic Probe for Logic Analyzer http://cp.literature.agilent.com/litweb/pdf/5989-0423EN.pdf • ...
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R XC2C64A CoolRunner-II CPLD The Spartan CPLD. The CPLD is user programmable and available for customer applications. Portions of the CPLD are reserved to coordinate behavior between the various FPGA configuration memories, namely the Xilinx Platform Flash PROM and the ...
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Chapter 16: XC2C64A CoolRunner-II CPLD JP10 WDT_EN Spartan-3E FPGA (N18) (P18) (F17) (F18) (G16) (T10) (V11) (M10) (D10) (R17) DONE PROG_B (H16) (C9) (U16) (A11) (N11) (V12) (V13) (T12) A[23:20] A[19:0] Figure 16-1: XC2C64A CoolRunner-II CPLD Controls Master Serial and ...
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R UCF Location Constraints There are two sets of constraints listed below XC2C64A CoolRunner-II CPLD. FPGA Connections to CPLD Figure 16-2 including the I/O pin assignment and the I/O standard used. NET "XC_CMD<1>" NET "XC_CMD<0>" NET "XC_D<2>" NET "XC_D<1>" NET ...
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Chapter 16: XC2C64A CoolRunner-II CPLD Related Resources • CoolRunner-II CPLD Family Data Sheet http://www.xilinx.com/support/documentation/data_sheets/ds090.pdf • XC2C64A CoolRunner-II CPLD Data Sheet http://www.xilinx.com/support/documentation/data_sheets/ds311.pdf • Default XC2C64A CPLD Design for Spartan-3E Starter Kit Board http://www.xilinx.com/s3estarter 130 www.xilinx.com Spartan-3E FPGA Starter Kit Board User ...
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R DS2432 1-Wire SHA-1 EEPROM The Spartan an integrated SHA-1 engine. As shown in Maxim 1-Wire interface, which as the name implies, cleverly uses a single wire for power and serial communication. The DS2432 EEPROM offers one of many possible ...
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Chapter 17: DS2432 1-Wire SHA-1 EEPROM 132 www.xilinx.com Spartan-3E FPGA Starter Kit Board User Guide UG230 (v1.2) January 20, 2011 R ...
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R Schematics This appendix provides the following circuit board schematics: • “FX2 Expansion Header, 6-pin Headers, and Connectorless Probe Header” • “RS-232 Ports, VGA Port, and PS/2 Port” • “Ethernet PHY, Magnetics, and RJ-11 Connector” • “Voltage Regulators” • “FPGA ...
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Appendix A: Schematics FX2 Expansion Header, 6-pin Headers, and Connectorless Probe Header Headers J1, J2, and J4 are six-pin connectors compatible with the Digilent Accessory board format. Headers J3A and J3B are the connections to the FX2 expansion connector located ...
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R Spartan-3E FPGA Starter Kit Board User Guide UG230 (v1.2) January 20, 2011 FX2 Expansion Header, 6-pin Headers, and Connectorless Probe Header Figure A-1: Schematic Sheet 1 www.xilinx.com UG230_Aa_01_021806 135 ...
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Appendix A: Schematics RS-232 Ports, VGA Port, and PS/2 Port IC2 is the Maxim LVTTL to RS-232 level converter. One of the serial channels connects to a female DB9 DCE connector (J9) and the other connects to a male DB9 ...
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R Spartan-3E FPGA Starter Kit Board User Guide UG230 (v1.2) January 20, 2011 RS-232 Ports, VGA Port, and PS/2 Port Figure A-2: Schematic Sheet 2 www.xilinx.com UG230_Aa_02_021806 137 ...
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Appendix A: Schematics Ethernet PHY, Magnetics, and RJ-11 Connector IC6 is an SMSC 10/100 Ethernet PHY, with its associated 25 MHz oscillator. The PHY requires an Ethernet MAC implemented within the FPGA. J19 is the RJ-11 Ethernet connector associated with ...
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R Spartan-3E FPGA Starter Kit Board User Guide UG230 (v1.2) January 20, 2011 Ethernet PHY, Magnetics, and RJ-11 Connector Figure A-3: Schematic Sheet 4 www.xilinx.com UG230_Aa_03_021806 139 ...
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Appendix A: Schematics Voltage Regulators IC7 is a Texas Instruments TPS75003 to the FPGA’s VCCINT supply input, 2.5V to the FPGA’s VCCAUX supply input, and 3.3V to other components on the board and to the FPGA’s VCCO supply inputs on ...
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R Spartan-3E FPGA Starter Kit Board User Guide UG230 (v1.2) January 20, 2011 Figure A-4: Schematic Sheet 5 www.xilinx.com Voltage Regulators UG230_Aa_04_021806 141 ...
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Appendix A: Schematics FPGA Configurations Settings, Platform Flash PROM, SPI Serial Flash, JTAG Connections IC10MISC represents the various FPGA configuration connections. IC11 Mbit XCF04S Platform Flash PROM. Landing pads for a second XCF04S PROM is shown as ...
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R FPGA Configurations Settings, Platform Flash PROM, SPI Serial Flash, JTAG Connections Spartan-3E FPGA Starter Kit Board User Guide UG230 (v1.2) January 20, 2011 Figure A-5: Schematic Sheet 6 www.xilinx.com UG230_Aa_05_021806 143 ...
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Appendix A: Schematics FPGA I/O Banks 0 and 1, Oscillators IC10B0 represents the connections to I/O Bank 0 on the FPGA. The VCCO input to Bank 0 is 3.3V by default, but can be set to 2.5V using jumper JP9. ...
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R Spartan-3E FPGA Starter Kit Board User Guide UG230 (v1.2) January 20, 2011 Figure A-6: Schematic Sheet 7 www.xilinx.com FPGA I/O Banks 0 and 1, Oscillators UG230_Aa_06_021806 145 ...
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Appendix A: Schematics FPGA I/O Banks 2 and 3 IC10B2 represents the connections to I/O Bank 2 on the FPGA. Some of the I/O Bank 2 connections are used for FPGA configuration and are listed as IC10MISC. IC10B3 represents the ...
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R Spartan-3E FPGA Starter Kit Board User Guide UG230 (v1.2) January 20, 2011 Figure A-7: Schematic Sheet 8 www.xilinx.com FPGA I/O Banks 2 and 3 UG230_Aa_07_021806 147 ...
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Appendix A: Schematics Power Supply Decoupling IC10PWR represents the various voltage supply inputs to the FPGA and shows the power decoupling network. Jumper JP9 defines the voltage applied to VCCO on I/O Bank 0. The default setting is 3.3V. See ...
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R Spartan-3E FPGA Starter Kit Board User Guide UG230 (v1.2) January 20, 2011 Figure A-8: Schematic Sheet 9 www.xilinx.com Power Supply Decoupling UG230_Aa_08_021806 149 ...
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Appendix A: Schematics XC2C64A CoolRunner-II CPLD IC18 is a Xilinx XC2C64A CoolRunner™-II CPLD. The CPLD primarily provides additional flexibility when configuring the FPGA from parallel NOR Flash and during MultiBoot configurations. When the CPLD is loaded with the appropriate design, ...
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R Spartan-3E FPGA Starter Kit Board User Guide UG230 (v1.2) January 20, 2011 Figure A-9: Schematic Sheet 10 www.xilinx.com XC2C64A CoolRunner-II CPLD UG230_Aa_09_021806 151 ...
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Appendix A: Schematics Linear Technology ADC and DAC IC19 is a Linear Technology LTC1407A-1 two-channel ADC. IC20 is a Linear Technology LTC6912 programmable pre-amplifier (AMP) to condition the analog inputs to the ADC. See Chapter 10, “Analog Capture Circuit,” IC21 ...
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R Spartan-3E FPGA Starter Kit Board User Guide UG230 (v1.2) January 20, 2011 Figure A-10: Schematic Sheet 11 www.xilinx.com Linear Technology ADC and DAC UG230_Aa_10_021806 153 ...
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Appendix A: Schematics Intel StrataFlash Parallel NOR Flash Memory and Micron DDR SDRAM IC22 is a 128 Mbit (16 Mbyte) Intel StrataFlash parallel NOR Flash PROM. See “Intel StrataFlash Parallel NOR Flash PROM,” IC23 is a 512 Mbit (64 Mbyte) ...
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R Spartan-3E FPGA Starter Kit Board User Guide UG230 (v1.2) January 20, 2011 Intel StrataFlash Parallel NOR Flash Memory and Micron DDR SDRAM Figure A-11: Schematic Sheet 12 www.xilinx.com UG230_Aa_11_021806 155 ...
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Appendix A: Schematics Buttons, Switches, Rotary Encoder, and Character LCD SW0, SW1, SW2, and SW3 are slide switches. Push-button switches and N are located around the ROT1 push-button switch/rotary encoder. LD0 through LD7 are discrete LEDs. See ...
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R Spartan-3E FPGA Starter Kit Board User Guide UG230 (v1.2) January 20, 2011 Buttons, Switches, Rotary Encoder, and Character LCD Figure A-12: Schematic Sheet 13 www.xilinx.com UG230_Aa_12_021806 157 ...
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Appendix A: Schematics DDR SDRAM Series Termination and FX2 Connector Differential Termination Resistors R160 through R201 represent the series termination resistors for the DDR SDRAM. See Resistors R202 through R210 are not loaded on the board. These landing pads provide ...
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R DDR SDRAM Series Termination and FX2 Connector Differential Termination Spartan-3E FPGA Starter Kit Board User Guide UG230 (v1.2) January 20, 2011 Figure A-13: Schematic Sheet 14 www.xilinx.com UG230_Aa_13_021806 159 ...
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Appendix A: Schematics 160 www.xilinx.com Spartan-3E FPGA Starter Kit Board User Guide UG230 (v1.2) January 20, 2011 R ...
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R Example User Constraints File (UCF) ##################################################### ### SPARTAN-3E STARTER KIT BOARD CONSTRAINTS FILE ##################################################### # ==== Analog-to-Digital Converter (ADC) ==== # some connections shared with SPI Flash, DAC, ADC, and AMP NET "AD_CONV" LOC = "P11" | IOSTANDARD = ...
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Appendix B: Example User Constraints File (UCF) NET "E_MDIO" LOC = "U5" NET "E_RX_CLK" LOC = "V3" NET "E_RX_DV" LOC = "V2" NET "E_RXD<0>" LOC = "V8" NET "E_RXD<1>" LOC = "T11" | IOSTANDARD = LVCMOS33 ; NET "E_RXD<2>" LOC ...
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R NET "FX2_IO<27>" LOC = "A16" | IOSTANDARD = LVCMOS33 NET "FX2_IO<28>" LOC = "B16" | IOSTANDARD = LVCMOS33 NET "FX2_IO<29>" LOC = "E13" | IOSTANDARD = LVCMOS33 NET "FX2_IO<30>" LOC = "C4" NET "FX2_IO<31>" LOC = "B11" | IOSTANDARD ...
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Appendix B: Example User Constraints File (UCF) NET "LED<6>" LOC = "E9" NET "LED<7>" LOC = "F9" # ==== PS/2 Mouse/Keyboard Port (PS2) ==== NET "PS2_CLK" LOC = "G14" | IOSTANDARD = LVCMOS33 NET "PS2_DATA" LOC = "G13" | IOSTANDARD ...
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R NET "SD_LDM" LOC = "J2" | IOSTANDARD = SSTL2_I ; NET "SD_LDQS" LOC = "L6" | IOSTANDARD = SSTL2_I ; NET "SD_RAS" LOC = "C1" | IOSTANDARD = SSTL2_I ; NET "SD_UDM" LOC = "J1" | IOSTANDARD = SSTL2_I ...
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Appendix B: Example User Constraints File (UCF) NET "SF_OE" LOC = "C18" | IOSTANDARD = LVCMOS33 NET "SF_STS" LOC = "B18" | IOSTANDARD = LVCMOS33 ; NET "SF_WE" LOC = "D17" | IOSTANDARD = LVCMOS33 # ==== STMicro SPI serial ...