HW-SPAR3E-SK-UK-G Xilinx Inc, HW-SPAR3E-SK-UK-G Datasheet - Page 87

• Manufacturer Part Number: HW-SPAR3E-SK-UK-G
• Description: KIT STARTER SPARTAN-3E
• Manufacturer: Xilinx Inc

Specifications of HW-SPAR3E-SK-UK-G

• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Development Tool Type: Hardware / Software - Starter Kit
• Mcu Supported Families: Spartan-3E
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: HW-SPAR3E-SK-US-UK-G; HW-SPAR3E-SK-US-UK-G

Shared Connections
Spartan-3E FPGA Starter Kit Board User Guide
UG230 (v1.2) January 20, 2011
Character LCD
Xilinx XC2C64A CPLD
SPI Data Line
R
Besides the connections to the FPGA, the StrataFlash memory shares some connections to
other components.
The character LCD uses a four-bit data interface. The display data connections are also
shared with the SF_D<11:8> signals on the StrataFlash PROM. As shown in
FPGA controls access to the StrataFlash PROM or the character LCD using the SF_CE0 and
LCD_RW signals.
Table 11-2: FPGA Control for StrataFlash and LCD
The Xilinx XC2C64A CoolRunner™-II CPLD controls the five upper StrataFlash address
lines, SF_A<24:20> during configuration. The four upper BPI-mode address lines from the
FPGA, A<23:20> are not connected. Instead, four FPGA user-I/O pins connect to the
StrataFlash PROM upper address lines SF_A<23:0>. See
CoolRunner-II CPLD”
The most-significant address line, SF_A<24>, is not physically used on the 16 Mbyte
StrataFlash PROM. It is provided for upward migration to a larger StrataFlash PROM in
the same package footprint. Likewsie, the SF_A<24> signal is also connected to the
FX2_IO<32> signal on the FX2 expansion connector.
The least-significant StrataFlash data line, SF_D<0>, is shared with data output signals
from serial SPI peripherals, SPI_MISO, and the serial output from the Platform Flash
PROM as shown in
only one data source is active at any time.
Table 11-3: Possible Contention on SPI_MISO (SF_D<0>) Data
FPGA_M2 = Low
FPGA_M1 = Low
FPGA_M0 = Low
INIT_B = High
SF_CE0 = Low
SF_OE = Low
AD_CONV = High
SPI_SCK
DAC_CS = Low
SPI_SCK
SF_CE0
Condition
1
0
LCD_RW
Table
for more information.
Platform Flash outputs data on D0.
StrataFlash outputs data.
Serial data is clocked out of the A/D converter
DAC outputs previous command in response to SPI_SCK transitions.
1
0
11-3. To avoid contention, the FPGA application must ensure that
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The FPGA reads from the character LCD.
The FPGA accesses the StrataFlash PROM.
Function
Function
Chapter 16, “XC2C64A
Shared Connections
Table
11-2, the
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