HW-SPAR3E-SK-UK-G Xilinx Inc, HW-SPAR3E-SK-UK-G Datasheet - Page 129

• Manufacturer Part Number: HW-SPAR3E-SK-UK-G
• Description: KIT STARTER SPARTAN-3E
• Manufacturer: Xilinx Inc

Specifications of HW-SPAR3E-SK-UK-G

• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Development Tool Type: Hardware / Software - Starter Kit
• Mcu Supported Families: Spartan-3E
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: HW-SPAR3E-SK-US-UK-G; HW-SPAR3E-SK-US-UK-G

UCF Location Constraints
Spartan-3E FPGA Starter Kit Board User Guide
UG230 (v1.2) January 20, 2011
FPGA Connections to CPLD
CPLD
R
There are two sets of constraints listed below
XC2C64A CoolRunner-II CPLD.
Figure 16-2
including the I/O pin assignment and the I/O standard used.
Figure 16-3
and the I/O standard used.
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# SF_A<24> is the same as FX2_IO<32>
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# SF_A<24> is the same as FX2_IO<32>
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Figure 16-2: UCF Location Constraints for FPGA Connections to CPLD
"XC_CMD<1>"
"XC_CMD<0>"
"XC_D<2>"
"XC_D<1>"
"XC_D<0>"
"FPGA_M2"
"FPGA_M1"
"FPGA_M0"
"XC_CPLD_EN"
"XC_TRIG"
"XC_GCK0"
"GCLK10"
"SPI_SCK"
"SF_A<24>"
"SF_A<23>"
"SF_A<22>"
"SF_A<21>"
"SF_A<20>"
"XC_WDT_EN"
"XC_CMD<1>"
"XC_CMD<0>"
"XC_D<2>"
"XC_D<1>"
"XC_D<0>"
"FPGA_M2"
"FPGA_M1"
"FPGA_M0"
"XC_CPLD_EN"
"XC_TRIG"
"XC_DONE"
"XC_PROG_B"
"XC_GCK0"
"GCLK10"
"SPI_SCK"
"SF_A<24>"
"SF_A<23>"
"SF_A<22>"
"SF_A<21>"
"SF_A<20>"
Figure 16-3: UCF Location Constraints for the XC2C64A CPLD
provides the UCF constraints for the FPGA connections to the CPLD ,
provides the UCF constraints for the CPLD , including the I/O pin assignment
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www.xilinx.com
= "N18" |
= "P18" |
= "F17" |
= "F18" |
= "G16" |
= "T10" |
= "V11" |
= "M10" |
= "B10" |
= "R17" |
= "H16" |
= "C9"
= "U16" |
= "A11" |
= "N11" |
= "V12" |
= "V13" |
= "T12" |
= "P16" |
= "P30" |
= "P29" |
= "P36" |
= "P34" |
= "P33" |
= "P8"
= "P6"
= "P5"
= "P42" |
= "P41" |
= "P40" |
= "P39" |
= "P43" |
= "P1"
= "P44" |
= "P23" |
= "P22" |
= "P21" |
= "P20" |
= "P19" |
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IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
–
one for the Spartan-3E FPGA and one for the
= LVCMOS33
= LVCMOS33
= LVCMOS33
= LVCMOS33
= LVCMOS33
= LVCMOS33
= LVCMOS33
= LVCMOS33
= LVCMOS33
= LVCMOS33 ;
= LVCMOS33
= LVCMOS33
= LVCMOS33
= LVCMOS33
= LVCMOS33
= LVCMOS33
= LVCMOS33
= LVCMOS33
= LVCMOS33 ;
= LVCMOS33 |
= LVCMOS33 |
= LVCMOS33 |
= LVCMOS33 |
= LVCMOS33 |
= LVCMOS33 |
= LVCMOS33 |
= LVCMOS33 |
= LVCMOS33 |
= LVCMOS33 |
= LVCMOS33 |
= LVCMOS33 |
= LVCMOS33 |
= LVCMOS33 |
= LVCMOS33 |
= LVCMOS33 |
= LVCMOS33 |
= LVCMOS33 |
= LVCMOS33 |
= LVCMOS33 |
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SLEW
SLEW
SLEW
SLEW
SLEW
SLEW
SLEW
SLEW
SLEW
SLEW
SLEW
SLEW
SLEW
SLEW
SLEW
SLEW
SLEW
SLEW
SLEW
SLEW
DRIVE
DRIVE
DRIVE
DRIVE
DRIVE
DRIVE
DRIVE
DRIVE
DRIVE
DRIVE
DRIVE
DRIVE
DRIVE
DRIVE
DRIVE
DRIVE
DRIVE
UCF Location Constraints
= SLOW ;
= SLOW ;
= SLOW ;
= SLOW ;
= SLOW ;
= SLOW ;
= SLOW ;
= SLOW ;
= SLOW ;
= SLOW ;
= SLOW ;
= SLOW ;
= SLOW ;
= SLOW ;
= SLOW ;
= SLOW ;
= SLOW ;
= SLOW ;
= SLOW ;
= SLOW ;
= 4
= 4
= 4
= 4
= 4
= 4
= 4
= 4
= 4
= 4
= 4
= 4
= 4
= 4
= 4
= 4
= 4
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SLEW
SLEW
SLEW
SLEW
SLEW
SLEW
SLEW
SLEW
SLEW
SLEW
SLEW
SLEW
SLEW
SLEW
SLEW
SLEW
SLEW
= SLOW ;
= SLOW ;
= SLOW ;
= SLOW ;
= SLOW ;
= SLOW ;
= SLOW ;
= SLOW ;
= SLOW ;
= SLOW ;
= SLOW ;
= SLOW ;
= SLOW ;
= SLOW ;
= SLOW ;
= SLOW ;
= SLOW ;
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