HW-SPAR3E-SK-UK-G Xilinx Inc, HW-SPAR3E-SK-UK-G Datasheet - Page 112

• Manufacturer Part Number: HW-SPAR3E-SK-UK-G
• Description: KIT STARTER SPARTAN-3E
• Manufacturer: Xilinx Inc

Specifications of HW-SPAR3E-SK-UK-G

• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Development Tool Type: Hardware / Software - Starter Kit
• Mcu Supported Families: Spartan-3E
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: HW-SPAR3E-SK-US-UK-G; HW-SPAR3E-SK-US-UK-G

Chapter 14: 10/100 Ethernet Physical Layer Interface
Ethernet PHY Connections
112
The FPGA connects to the LAN83C185 Ethernet PHY using a standard Media Independent
Interface (MII), as shown in
signals, including the FPGA pin number, appears in
Table 14-1: FPGA Connections to the LAN83C185 Ethernet PHY
Signal Name
E_TX_CLK
E_RXD<4>
E_RXD<3>
E_RXD<2>
E_RXD<1>
E_RXD<0>
E_TXD<4>
E_TXD<3>
E_TXD<2>
E_TXD<1>
E_TXD<0>
E_RX_DV
E_TX_EN
Spartan-3E FPGA
See Table
See Table
Figure 14-2: FPGA Connects to Ethernet PHY via MII
FPGA Pin
Number
(P15)
(U14)
(U13)
(R4)
(U6)
(U5)
(T7)
(V2)
(V3)
(P9)
U14
V14
U11
T15
R11
P15
T11
R6
R5
V8
V2
T5
T7
www.xilinx.com
Figure
E_TXD<3:0>
E_TX_EN
E_TXD<4>
E_TX_CLK
E_RXD<3:0>
E_RX_DV
E_RXD<4>
E_RX_CLK
E_CRS
E_COL
E_MDC
E_MDIO
Transmit Data to the PHY. E_TXD<4> is also the MII
Transmit Error.
Transmit Enable.
Transmit Clock. 25 MHz in 100Base-TX mode, and 2.5 MHz
in 10Base-T mode.
Receive Data from PHY.
Receive Data Valid.
14-2. A more detailed description of the interface
Spartan-3E FPGA Starter Kit Board User Guide
TXD[3:0]
TX_EN
TXD4/TX_ER
TX_CLK
RXD[3:0]
RX_DV
RXD4/RX_ER
RX_CLK
CRS
COL
MDC
MDIO
10/100 Ethernet PHY
SMSC LAN83C185
Table
Function
14-1.
UG230 (v1.2) January 20, 2011
UG230_c14_02_022706
25.000 MHz
Connector
RJ-45
R