KP125 EVAL BOARD Infineon Technologies, KP125 EVAL BOARD Datasheet - Page 28

• Manufacturer Part Number: KP125 EVAL BOARD
• Description: BOARD EVALUATION KP125
• Manufacturer: Infineon Technologies
• Type: Pressure Sensorr

Specifications of KP125 EVAL BOARD

• Contents: Fully Assembled Evaluation Board
• For Use With/related Products: KP125
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: KP125EVALBOARDIN

7.3
The content of the EEPROM registers should not be changed. In this User’s Manual only the content of the control
registers is described.
After startup the chip is in normal operation mode and does not react to any read or write command except the
test mode activation sequence on the serial interface. Test mode is enabled by writing “2CEh” to the CSR register
(see
EEP refresh or by triggering CALC_FEC in EEP control register and during startup. Deactivation followed by
activation of the FEC does not recalculate the FEC-flags. Serial interface does not transmit any status information
when test mode is not activated. Status bits cannot be written.
Figure 28
1) Clamping only available for KP126
User’s Manual
bit
9
8
7
6
5
4
3
2:1
0
Figure
reserved
function
SPI_ERR
FEC_ACT
FEC_ERR
CLAMPED_H 0
CLAMPED_L 0
MARG_FAIL
reserved
TSTMD_ACT 0
28) address. Writing any other sequence disables test mode. Status bits 7/8 (FEC) are updated after
Register Description
Address 0x08: CSR Register
value
0
1
0
1
0
1
1
1
0
1
0
1
description
last SPI transaction OK
last SPI transaction not OK
FEC not activated
FEC activated
FEC ok
FEC error
no clamping
upper clamping level exceeded reset only by a read access
no clamping
lower clamping level under-
run
margin threshold not reached
during last test
margin threshold reached
during last test; at least one
EEP register toggled
test mode inactive
test mode activated
1)
28
Digital Interface for EEPROM access
Evalkit for Pressure Sensors
remark
reset only by a faultless read
access
no parity error in EEP array
or FEC disabled
detected and corrected
uncorrectable error detected
in EEP array, VOUT will be
set to GND level
reset only by a read access
reset only by a read access
one parity error in EEP array
Rev. 1.1, 2007-11-23
KP12x Kit