isp1562 NXP Semiconductors, isp1562 Datasheet
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isp1562 Summary of contents
Page 1
... Windows standard OHCI and EHCI drivers that are present in Windows XP, Windows 2000 and Red Hat Linux. The ISP1562 directly interfaces to any 32-bit, 33 MHz PCI bus. Its PCI pins can source 3.3 V. The PCI interface fully complies with PCI Local Bus Specification Rev. 2.2 . ...
Page 2
... Type number Package Name Description ISP1562BE LQFP100 plastic low profile quad flat package; 100 leads; body 14 ISP1562_2 Product data sheet and V aux(3V3) CC Rev. 02 — 1 March 2007 ISP1562 HS USB PCI Host Controller Version 14 1.4 mm SOT407-1 © NXP B.V. 2007. All rights reserved ...
Page 3
... V I(VREG3V3) VOLTAGE 18, 43, 58 REGULATOR REG1V8 V CC(I/O) DETECT 74 XTAL1 XOSC 75 PLL XTAL2 Fig 1. Block diagram SCL SDA 96 GLOBAL CONTROL ISP1562 OHCI OHCI (FUNCTION 0) (FUNCTION 1) RAM RAM PORT ROUTER CORE RESET_N ATX1 V CC ORIGINAL Hi-SPEED ORIGINAL CORE USB ATX USB ATX USB ATX 86, 93 ...
Page 4
... AD[29 AD[28] 15 AD[27 I(VREG3V3) GNDA 17 18 REG1V8 GNDD 19 AD[26] 20 AD[25 AD[24] C/BE#[3] 23 IDSEL CC(I/O) Fig 2. Pin configuration ISP1562_2 Product data sheet ISP1562BE Rev. 02 — 1 March 2007 ISP1562 HS USB PCI Host Controller 75 XTAL2 74 XTAL1 73 AUX1V8 72 GNDA 71 V CC(I/O) 70 AD[0] 69 AD[1] 68 AD[2] 67 AD[3] 66 AD[4] 65 AD[5] 64 GNDD 63 AD[6] 62 AD[7] 61 GNDA ...
Page 5
... PCI pad; 3.3 V signaling 21 I/O bit 25 of multiplexed PCI address and data PCI pad; 3.3 V signaling 22 I/O bit 24 of multiplexed PCI address and data PCI pad; 3.3 V signaling Rev. 02 — 1 March 2007 ISP1562 HS USB PCI Host Controller Table 118 © NXP B.V. 2007. All rights reserved ...
Page 6
... PCI stop; indicates that the current target is requesting the master to stop the current transaction PCI pad; 3.3 V signaling 42 I/O PCI CLKRUN signal; pull-down to ground through resistor PCI pad; 3.3 V signaling; open-drain Rev. 02 — 1 March 2007 ISP1562 HS USB PCI Host Controller © NXP B.V. 2007. All rights reserved ...
Page 7
... PCI pad; 3.3 V signaling 61 - analog ground 62 I/O bit 7 of multiplexed PCI address and data PCI pad; 3.3 V signaling 63 I/O bit 6 of multiplexed PCI address and data PCI pad; 3.3 V signaling Rev. 02 — 1 March 2007 ISP1562 HS USB PCI Host Controller © NXP B.V. 2007. All rights reserved ...
Page 8
... USB downstream port 2 (digital) 3.3 V input pad; push-pull; CMOS 88 O power enable for the USB downstream port 2 3.3 V output pad slew rate control; CMOS; open-drain 89 - analog ground Rev. 02 — 1 March 2007 ISP1562 HS USB PCI Host Controller 1 %) © NXP B.V. 2007. All rights reserved ...
Page 9
... PCI pad; 3.3 V signaling; open-drain 100 - 3.3 V auxiliary supply voltage; used to power pads; add a 100 nF decoupling capacitor 2 C-bus is not used. Rev. 02 — 1 March 2007 ISP1562 HS USB PCI Host Controller [2] [2] © NXP B.V. 2007. All rights reserved ...
Page 10
... Mbit/s), full-speed (12 Mbit/s) and low-speed (1.5 Mbit/s). 7.5 Power management The ISP1562 provides an advanced power management capability interface that is compliant with PCI Bus Power Management Interface Specification Rev. 1.1 . Power is controlled and managed by the interaction between drivers and PCI registers. ...
Page 11
... Power supply Figure 4 ISP1562_2 Product data sheet shows a possible curve of V CC(I/ typically 1.2 V. POR(trip) shows the ISP1562 power supply connection. Rev. 02 — 1 March 2007 ISP1562 HS USB PCI Host Controller with dips and t4 to t5. At t0, POR will V CC(I/O) V POR(trip ...
Page 12
... REG1V8 43, 58 100 17, 19, 32, 46, 49, 61, 64, 72, 76, 80, 82, 84, 89, 91, 94, 95 GND is not present on PCI, the pin should be connected to PCI 3.3 V. aux(3V3) Rev. 02 — 1 March 2007 ISP1562 HS USB PCI Host Controller PCI 3.3 V 100 nF PCI 3.3 V 100 nF (1) PCI V aux(3V3) 100 nF (1) PCI V ...
Page 13
... PCI configuration space PCI Local Bus Specification Rev. 2.2 requires that each of the three PCI functions of the ISP1562 provides its own PCI configuration registers, which can vary in size. In addition to the basic PCI configuration header registers, these functions implement capability registers to support power management ...
Page 14
... D282 0001h D282 0001h [2] 0000 XX00h 0000 XX00h Table 4. ISP1562 [1] Func2 EHCI 0080 0000h 0000 0000h 0000 0000h 1562 1131h 0000 0000h 0000 00DCh 0000 0000h 1002 0100h 0000 8000h 0007 2020h FE82 0001h ...
Page 15
... X* Device ID: This register value is defined by NXP Semiconductors to identify the Hi-Speed USB Host Controller IC product. For the ISP1562, NXP Semiconductors has defined OHCI functions as 1561h, and the EHCI function as 1562h. 6. When logic 0 is written to this register, the device is logically disconnected from ...
Page 16
... IO Space: Controls the response of a device to I/O space accesses. 0 — Disables the device response. State after RST# is logic 0. 1 — Allows the device to respond to I/O space accesses. ISP1562_2 Product data sheet Rev. 02 — 1 March 2007 ISP1562 HS USB PCI Host Controller © NXP B.V. 2007. All rights reserved ...
Page 17
... 66MC Rev. 02 — 1 March 2007 HS USB PCI Host Controller Table STA DEVSELT[1: reserved © NXP B.V. 2007. All rights reserved. ISP1562 8 MDPE ...
Page 18
... SCC[7: RLPI[7: Rev. 02 — 1 March 2007 HS USB PCI Host Controller …continued Table 10 0Ch 03h [ ISP1562 Table © NXP B.V. 2007. All rights reserved ...
Page 19
... Latency Timer: This byte identifies the latency timer Rev. 02 — 1 March 2007 HS USB PCI Host Controller Table 13 shows the bit Table 15 HT[6: ISP1562 © NXP B.V. 2007. All rights reserved ...
Page 20
... Therefore, BAR0[31:12] is assigned to the two OHCI ports, and BAR0[31:8] is assigned to the EHCI port. Value Description 1131h* Subsystem Vendor ID: 1131h is the subsystem Vendor ID assigned to NXP Semiconductors. Table 19. Rev. 02 — 1 March 2007 ISP1562 HS USB PCI Host Controller Table 17. Table 18. © NXP B.V. 2007. All rights reserved ...
Page 21
... DCh* Capabilities Pointer: EHCI efficiently manages power using this register. This Power Management register is allocated at offset DCh. Only one Host Controller is needed to manage power in the ISP1562. Description Interrupt Line: Indicates which IRQ is used to report interrupt from the ISP1562. Table 22. Value Description 01h* Interrupt Pin: INTA# is the default interrupt pin used by the ISP1562 ...
Page 22
... MIN_GNT used to specify how long a burst period the device needs, assuming a clock rate of 33 MHz. Value Description [1] X* MAX_LAT used to specify how often the device needs to gain access to the PCI bus. Rev. 02 — 1 March 2007 ISP1562 HS USB PCI Host Controller Table 23. Table 24. © NXP B.V. 2007. All rights reserved ...
Page 23
... Serial Bus Specification Release Number: This register value is to identify Universal Serial Bus Specification Rev. 2.0 . All other combinations are reserved. Table 27 R/W R/W Rev. 02 — 1 March 2007 ISP1562 HS USB PCI Host Controller Table 25 FLADJ[5: R/W R/W R/W Table 29 ...
Page 24
... Capability Identifier (CAP_ID) Next Item Pointer (NEXT_ITEM_PTR) Power Management Capabilities (PMC) Power Management Control/Status (PMCSR) Power Management Control/Status PCI-to-PCI Bridge Support Extensions (PMCSR_BSE) Data Rev. 02 — 1 March 2007 ISP1562 HS USB PCI Host Controller SOF cycle time (480 MHz) 59488 59504 59520 : 59984 ...
Page 25
... This register provides information on the capabilities of the PME_S[4:0] [ DSI reserved Rev. 02 — 1 March 2007 ISP1562 HS USB PCI Host Controller Table 33 D2_S D1_S [1] [ PMI VER[2: ...
Page 26
... Data register, bit assignments cold are: aux(3V3) Rev. 02 — 1 March 2007 ISP1562 HS USB PCI Host Controller current requirement reporting. © NXP B.V. 2007. All rights reserved ...
Page 27
... X is indeterminate at the time of initial operating system boot the cold . cold . If the function supports the PME# generation from D3 cold , then this bit is sticky and must be explicitly cleared by the cold Rev. 02 — 1 March 2007 ISP1562 HS USB PCI Host Controller D_S[3: ...
Page 28
... R R Table 40 . hot , its secondary bus’s PCI hot , its secondary bus will have hot Resultant actions by bridge (either direct or indirect) none none ISP1562 Table 40 is enabled. are disabled. © NXP B.V. 2007. All rights reserved ...
Page 29
... Rev. 02 — 1 March 2007 HS USB PCI Host Controller …continued Resultant actions by bridge (either direct or indirect) clock stopped on secondary bus clock stopped and PCI V removed from secondary CC bus (B3 only); for definition of B2_B3#, see none ISP1562 Table 39. © NXP B.V. 2007. All rights reserved ...
Page 30
... LOW level on SDA during the ninth clock pulse on SCL. For detailed information, refer to The I 9.2 Hardware connections The ISP1562 can be connected to an external EEPROM through the I The hardware connections are shown in Fig 5. EEPROM connection diagram ISP1562_2 Product data sheet ...
Page 31
... NXP Semiconductors The slave address that the ISP1562 uses to access the EEPROM is 101 0000b. Page mode addressing is not supported. Therefore, pins A0, A1 and A2 of the EEPROM must be connected to ground (logic 0). 9.3 Information loading from EEPROM Figure 6 default values of device ID, vendor ID, subsystem VID and subsystem DID assigned to NXP Semiconductors by PCI-SIG will be loaded ...
Page 32
... HCCPARAMS HCSP-PORTROUTE1[31:0] HCSP-PORTROUTE2[59:32] reserved reserved reserved USBCMD USBSTS USBINTR FRINDEX reserved PERIODICLISTBASE ASYNCLISTADDR reserved reserved reserved reserved ISP1562 [1] Reset value Func2 EHCI 0100 0020h 0000 2192h 0000 0012h 0000 0010h 0000 0000h - - - 0008 0000h 0000 1000h 0000 0000h 0000 0000h - 0000 0000h ...
Page 33
... Reset values that are highlighted, for example, 0, are the ISP1562 implementation-specific reset values; and reset values that are not highlighted, for example, 0, are compliant with OHCI and EHCI specifications. For the OHCI Host Controller, there are only operational registers for the USB operation. ...
Page 34
... R/W R reserved R/W R [1] reserved R/W R BLE CLE R/W R/W Rev. 02 — 1 March 2007 ISP1562 HS USB PCI Host Controller [ R/W R R/W R/W R RWE RWC ...
Page 35
... HCD, processing of the periodic list does not occur after the next SOF. The Host Controller must check this bit before it starts processing the list. ISP1562_2 Product data sheet …continued Rev. 02 — 1 March 2007 ISP1562 HS USB PCI Host Controller © NXP B.V. 2007. All rights reserved ...
Page 36
... HcCommandStatus register reserved R/W R [1] reserved R/W R reserved R/W R [1] reserved R/W R/W Rev. 02 — 1 March 2007 ISP1562 HS USB PCI Host Controller …continued [ R/W R/W R R/W R R/W R/W R OCR BLF CLF 0 0 ...
Page 37
... R/W R/W ISP1562_2 Product data sheet Table 51) and the MIE (Master Interrupt Enable) bit is set. The HCD may R/W R/W Rev. 02 — 1 March 2007 ISP1562 HS USB PCI Host Controller Table 49. When an event occurs, the [1] reserved R/W R/W R/W © NXP B.V. 2007. All rights reserved. ...
Page 38
... ISP1562_2 Product data sheet reserved R/W R reserved R/W R FNO R/W R/W Rev. 02 — 1 March 2007 ISP1562 HS USB PCI Host Controller [ R/W R R/W R/W R WDH R/W ...
Page 39
... Product data sheet R/W R reserved R/W R reserved R/W R FNO R/W R/W Rev. 02 — 1 March 2007 ISP1562 HS USB PCI Host Controller Table 51 [1] reserved R/W R R/W R R/W R/W R ...
Page 40
... Access R/W R/W Bit 23 Symbol Reset 0 Access R/W R/W ISP1562_2 Product data sheet R/W R reserved R/W R/W Rev. 02 — 1 March 2007 ISP1562 HS USB PCI Host Controller …continued Table 53 [1] reserved R/W R R/W R/W R/W © NXP B.V. 2007. All rights reserved R/W 16 ...
Page 41
... Ignore 1 — Disables interrupt generation because of scheduling overrun. ISP1562_2 Product data sheet reserved R/W R FNO R/W R/W Rev. 02 — 1 March 2007 ISP1562 HS USB PCI Host Controller [ R/W R/W R WDH R/W R/W R/W © NXP B.V. 2007. All rights reserved. ...
Page 42
... R/W R HCCA[15: R/W R HCCA[7: R/W R reserved R/W R/W shows the bit allocation of the register. Rev. 02 — 1 March 2007 ISP1562 HS USB PCI Host Controller Table 55. The HCD determines alignment R/W R/W R R/W R/W R R/W R/W R/W 3 ...
Page 43
... reserved 59 ISP1562 © ...
Page 44
... R R Table 61 reserved ISP1562 © NXP B.V. 2007. All rights reserved ...
Page 45
... R/W R BHED[19:12 R/W R BHED[11: R/W R BHED[3: R/W R/W Table 65 BCED[27:20 R/W R/W Rev. 02 — 1 March 2007 ISP1562 HS USB PCI Host Controller R/W R/W R R/W R/W R R/W R/W R [1] reserved R/W R/W R ...
Page 46
... R/W R BCED[3: R/W R DH[27:20 R/W R DH[19:12 R/W R DH[11: R/W R/W Rev. 02 — 1 March 2007 ISP1562 HS USB PCI Host Controller R/W R/W R R/W R/W R [1] reserved R/W R/W R/W Table 67 shows the bit allocation R/W R/W R/W 19 ...
Page 47
... FI[7: R/W R/W Rev. 02 — 1 March 2007 HS USB PCI Host Controller 3 2 [1] reserved 0 0 R/W R/W R/W Table 69 FSMPS[14: R/W R/W R R/W R/W R FI[13: R/W R/W R R/W R/W R/W ISP1562 R/W © NXP B.V. 2007. All rights reserved ...
Page 48
... R/W R R/W R FR[7: R/W R/W Rev. 02 — 1 March 2007 HS USB PCI Host Controller [1] reserved R/W R R/W R/W R FR[13: R/W R/W R R/W R/W R/W ISP1562 R/W © NXP B.V. 2007. All rights reserved ...
Page 49
... ISP1562_2 Product data sheet reserved R/W R reserved R/W R R/W R FN[7: R/W R/W Rev. 02 — 1 March 2007 ISP1562 HS USB PCI Host Controller Table 73. It provides [ R/W R R/W R/W R FN[13: R/W R/W R ...
Page 50
... R/W R reserved R/W R R/W R P_S[7: R/W R reserved R/W R/W Rev. 02 — 1 March 2007 ISP1562 HS USB PCI Host Controller [ R/W R R/W R/W R P_S[13: R/W R/W R R/W R/W R ...
Page 51
... R/W contains the bit allocation of the HcRhDescriptorA register POTPGT[7: R/W R reserved R/W R [1] NOCP R/W R/W Rev. 02 — 1 March 2007 ISP1562 HS USB PCI Host Controller [ R/W R/W R LST[11: R/W R/W R R/W R/W R/W this field. The value is calculated by ...
Page 52
... Reset values are implementation-specific. ISP1562_2 Product data sheet NDP[7: Rev. 02 — 1 March 2007 ISP1562 HS USB PCI Host Controller ms. Table 81. These fields are written during © NXP B.V. 2007. All rights reserved. ...
Page 53
... Rev. 02 — 1 March 2007 HS USB PCI Host Controller R/W R R/W R/W R R/W R/W R R/W R/W R/W shows the bit allocation of the register [1] reserved R/W R/W R/W ISP1562 R/W © NXP B.V. 2007. All rights reserved ...
Page 54
... R/W R R/W R [1] reserved R/W R/W Rev. 02 — 1 March 2007 HS USB PCI Host Controller CCIC R/W R/W R [1] reserved R/W R/W R OCI R/W R/W R ISP1562 16 LPSC 0 R R/W 0 LPS 0 RW © NXP B.V. 2007. All rights reserved ...
Page 55
... R/W R [1] PRSC R/W R [1] reserved R/W R [1] PRS R/W R/W Rev. 02 — 1 March 2007 ISP1562 HS USB PCI Host Controller [ R/W R/W R OCIC PSSC PESC R/W R/W R LSDA R/W R/W R POCI PSS ...
Page 56
... On write Set Port Power: The HCD can write logic 1 to set the PPS (Port Power Status) bit. Writing logic 0 has no effect. Remark: This bit always reads logic 1 if power switching is not supported reserved - ISP1562_2 Product data sheet Rev. 02 — 1 March 2007 ISP1562 HS USB PCI Host Controller …continued © NXP B.V. 2007. All rights reserved ...
Page 57
... Status) bit. Writing logic 0 has no effect. The CCS bit is not affected by any write. Remark: This bit always reads logic 1 when the attached device is nonremovable (DeviceRemovable[NDP]). ISP1562_2 Product data sheet Rev. 02 — 1 March 2007 ISP1562 HS USB PCI Host Controller …continued © NXP B.V. 2007. All rights reserved ...
Page 58
... HCIVERSION[7: reserved CAPLENGTH[7: Rev. 02 — 1 March 2007 ISP1562 HS USB PCI Host Controller Table 87 ...
Page 59
... reserved N_CC[3: reserved PPC Rev. 02 — 1 March 2007 ISP1562 HS USB PCI Host Controller N_PCC[3: ...
Page 60
... Rev. 02 — 1 March 2007 HS USB PCI Host Controller …continued 91 reserved ISP1562 PFLF 64AC © NXP B.V. 2007. All rights reserved ...
Page 61
... R/W Bit 23 Symbol Reset 0 Access R/W R/W ISP1562_2 Product data sheet reserved R/W R ITC[7: R/W R/W Rev. 02 — 1 March 2007 ISP1562 HS USB PCI Host Controller …continued [ R/W R/W R R/W R/W R/W © NXP B.V. 2007. All rights reserved. Table R R ...
Page 62
... ISP1562_2 Product data sheet reserved R/W R ASE PSE R/W R/W Rev. 02 — 1 March 2007 ISP1562 HS USB PCI Host Controller [ R/W R/W R FLS[1:0] HC RESET R/W R/W R/W © ...
Page 63
... Address: Content of the base address register + 24h Bit 31 Symbol Reset 0 Access R/W R/W ISP1562_2 Product data sheet Table 95 reserved R/W R/W Rev. 02 — 1 March 2007 HS USB PCI Host Controller …continued R/W R/W ISP1562 R/W R/W © NXP B.V. 2007. All rights reserved ...
Page 64
... Product data sheet reserved R/W R RECL HCH IAA HSE R/W Rev. 02 — 1 March 2007 ISP1562 HS USB PCI Host Controller [ R/W R/W R [1] reserved R/W R/W R FLR PCD USB ERRINT ...
Page 65
... R/W R reserved R/W R reserved R/W R/W Rev. 02 — 1 March 2007 HS USB PCI Host Controller 97 [ R R R/W R/W ISP1562 R/W R R/W R R/W R/W © NXP B.V. 2007. All rights reserved ...
Page 66
... Reset 0 Access R/W R/W ISP1562_2 Product data sheet IAAE HSEE R/W R/W Table 99 reserved R/W R/W Rev. 02 — 1 March 2007 ISP1562 HS USB PCI Host Controller FLRE PCIE USBERR INTE R/W R R/W R/W R/W © NXP B.V. 2007. All rights reserved. 0 USBINTE 0 ...
Page 67
... Table 101 illustrates values of N based on the value of FLS[1:0] (bits the USBCMD register). Number elements 1024 512 256 reserved Table 102. Rev. 02 — 1 March 2007 ISP1562 HS USB PCI Host Controller [ R/W R/W R/W ...
Page 68
... LPL[26:19 R/W R/W Rev. 02 — 1 March 2007 HS USB PCI Host Controller R/W R/W R R/W R/W R [1] reserved 0 0 R/W R R/W R/W R/W Table 104 R/W R/W R/W ISP1562 R/W © NXP B.V. 2007. All rights reserved ...
Page 69
... R/W R reserved R/W R reserved R/W R reserved R/W R [1] reserved R/W R/W Rev. 02 — 1 March 2007 ISP1562 HS USB PCI Host Controller R/W R/W R R/W R/W R [1] reserved R/W R R/W R/W R ...
Page 70
... R/W R WKDS WKCNNT_ CNNT_E R/W R R/W R OCC OCA Rev. 02 — 1 March 2007 ISP1562 HS USB PCI Host Controller 1) where Port Number [ R/W R/W R PTC[3: R/W R/W R LS[1:0] reserved R/W R/W R ...
Page 71
... Undefined: Not a low-speed device, perform EHCI reset If the PP bit is logic 0, this field is undefined. 9 reserved - ISP1562_2 Product data sheet Port Number 1) where Port Number [1] [1] [1] Rev. 02 — 1 March 2007 ISP1562 HS USB PCI Host Controller © NXP B.V. 2007. All rights reserved ...
Page 72
... Product data sheet Port Number Software changes the FPR (Force Port Resume) bit to logic 0. Software changes the PR (Port Reset) bit to logic 1. [1] Rev. 02 — 1 March 2007 ISP1562 HS USB PCI Host Controller …continued 1) where Port Number [1] © NXP B.V. 2007. All rights reserved. ...
Page 73
... ECSC bit to be set. [1] These fields read logic 0, if the PP bit is logic 0. ISP1562_2 Product data sheet Port Number 1) where Port Number [1] [1] [1] Rev. 02 — 1 March 2007 ISP1562 HS USB PCI Host Controller …continued [1] © NXP B.V. 2007. All rights reserved ...
Page 74
... ISP1562 one high-speed device connected to the ISP1562 two high-speed devices connected to the ISP1562 no device connected to the ISP1562 one high-speed device connected to the ISP1562 two high-speed devices connected to the ISP1562 shows the current consumption in S1 and S3 suspend modes. Typ ...
Page 75
... T junction temperature j ISP1562_2 Product data sheet Conditions Min V < > CC(I/O) all pins (I < Conditions Min 3.0 3.0 3.0 3.0 3 Rev. 02 — 1 March 2007 ISP1562 HS USB PCI Host Controller Max Unit 0.5 +4.6 V 0.5 +4.6 V 0.5 +4.6 V 0.5 +4.6 V 0.5 +4.6 V 100 +125 C Typ Max Unit 3 ...
Page 76
... Conditions Conditions Conditions 0 V < V < CC(I/ 500 1500 A O Conditions squelch detected no squelch detected disconnect detected disconnect not detected Rev. 02 — 1 March 2007 ISP1562 HS USB PCI Host Controller Min Typ Max 2 0 Min Typ Max 2.0 - 3.6 ...
Page 77
... High-speed termination resistor disabled, pull-up resistor connected. Only during reset, when both the hub and device are capable of high-speed operation. ISP1562_2 Product data sheet Conditions Min 10 360 10 700 900 drive 2 0.8 2.8 0 0.8 1.3 Rev. 02 — 1 March 2007 ISP1562 HS USB PCI Host Controller …continued Typ Max - +10 - 440 - +10 [1] - 1100 [1] - 500 - - - 3 ...
Page 78
... Min Typ - 0 and the maximum rise time (300 ns), use OL 0. CC(I/O) Min Typ 1 - Min Typ 500 - 500 - 40.5 45 ISP1562 Max Unit - s 33 MHz - MHz 100 - pF 1. ppm Max Unit 250 ns Max Unit 4 V/ns Max Unit - 49.5 © NXP B.V. 2007. All rights reserved. ...
Page 79
... Conditions pF pF full-speed timing low-speed timing Conditions Rev. 02 — 1 March 2007 ISP1562 HS USB PCI Host Controller …continued Min Typ Max 479.76 - 480.24 124.9375 - 125.0625 1 - four high-speed bit times Min Typ ...
Page 80
... Rev. 02 — 1 March 2007 HS USB PCI Host Controller Min Typ Max [ [ 100 - - T cyc(PCICLK) t LOW(PCICLK) minimum value 0.4V CC(I/O) © NXP B.V. 2007. All rights reserved. ISP1562 Unit V/ns mV/ 004aaa604 ...
Page 81
... CC(I/O) t dZ(act) t d(act)Z crossover point extended differential data to SE0/EOP skew USBbit DEOP Rev. 02 — 1 March 2007 ISP1562 HS USB PCI Host Controller t h(PCICLK) inputs valid 0.6V 0.4V 0.2V (falling edge) (rising edge) 004aaa606 source EOP width: t EOPT receiver EOP width: t 004aaa704 © NXP B.V. 2007. All rights reserved. ...
Page 82
... JEDEC JEITA MS-026 Rev. 02 — 1 March 2007 HS USB PCI Host Controller detail 0.75 1.15 1 0.2 0.08 0.08 0.45 0.85 EUROPEAN PROJECTION ISP1562 SOT407 ( 0.85 0 ISSUE DATE 00-02-01 03-02-20 © NXP B.V. 2007. All rights reserved ...
Page 83
... Solder bath specifications, including temperature and impurities ISP1562_2 Product data sheet Rev. 02 — 1 March 2007 ISP1562 HS USB PCI Host Controller © NXP B.V. 2007. All rights reserved ...
Page 84
... Package reflow temperature ( C) 3 Volume (mm ) < 350 260 260 250 Figure 12. Rev. 02 — 1 March 2007 ISP1562 HS USB PCI Host Controller Figure 12) than a PbSn process, thus 350 220 220 350 to 2000 > 2000 260 260 250 245 245 245 © ...
Page 85
... Peripheral Component Interconnect PCI-Special Interest Group Phase-Locked Loop Power Management Power Management Capabilities Power Management Event Power-On Reset Power-On Self Test Rev. 02 — 1 March 2007 ISP1562 HS USB PCI Host Controller peak temperature time 001aac844 © NXP B.V. 2007. All rights reserved ...
Page 86
... V updated PCI reset timing section. Product data sheet Rev. 02 — 1 March 2007 ISP1562 HS USB PCI Host Controller Change notice Supersedes - ISP1562_1 description” SCL)”: added max value for V and min value for © NXP B.V. 2007. All rights reserved. ...
Page 87
... Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners C-bus — logo is a trademark of NXP B.V. http://www.nxp.com salesaddresses@nxp.com Rev. 02 — 1 March 2007 ISP1562 HS USB PCI Host Controller © NXP B.V. 2007. All rights reserved ...
Page 88
... Table 50. HcInterruptStatus - Host Controller Interrupt Status register bit description . . . . . . . . . . . . . 38 Table 51. HcInterruptEnable - Host Controller Interrupt Enable register bit allocation . . . . . . . . . . . . . . 39 Table 52. HcInterruptEnable - Host Controller Interrupt Enable register bit description . . . . . . . . . . . . . 39 Rev. 02 — 1 March 2007 ISP1562 HS USB PCI Host Controller continued >> © NXP B.V. 2007. All rights reserved ...
Page 89
... Table 97. USBINTR - USB Interrupt Enable register bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Table 98. USBINTR - USB Interrupt Enable register bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Table 99. FRINDEX - Frame Index register bit allocation 66 Table 100.FRINDEX - Frame Index register bit Rev. 02 — 1 March 2007 ISP1562 HS USB PCI Host Controller continued >> © NXP B.V. 2007. All rights reserved ...
Page 90
... Table 125.SnPb eutectic process (from J-STD-020C .84 Table 126.Lead-free process (from J-STD-020C .84 Table 127.Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . .85 Table 128.Revision history . . . . . . . . . . . . . . . . . . . . . . . .86 ISP1562_2 Product data sheet 2 C-bus interface 2 C-bus interface Rev. 02 — 1 March 2007 ISP1562 HS USB PCI Host Controller continued >> © NXP B.V. 2007. All rights reserved ...
Page 91
... Fig 10. USB source differential data-to-EOP transition skew and EOP width . . . . . . . . . . . . . .81 Fig 11. Package outline SOT407-1 (LQFP100 .82 Fig 12. Temperature profiles for large and small components . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 ISP1562_2 Product data sheet Rev. 02 — 1 March 2007 ISP1562 HS USB PCI Host Controller continued >> © NXP B.V. 2007. All rights reserved ...
Page 92
... HcRhStatus register . . . . . . . . . . . . . . . . . . . . 53 11.1.22 HcRhPortStatus[4:1] register . . . . . . . . . . . . . 55 11.2 EHCI controller capability registers . . . . . . . . 58 11.2.1 CAPLENGTH/HCIVERSION register 11.2.2 HCSPARAMS register . . . . . . . . . . . . . . . . . . 58 11.2.3 HCCPARAMS register . . . . . . . . . . . . . . . . . . 60 11.2.4 HCSP-PORTROUTE register 11.3 Operational registers of enhanced USB Host Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 11.3.1 USBCMD register Rev. 02 — 1 March 2007 ISP1562 HS USB PCI Host Controller continued >> © NXP B.V. 2007. All rights reserved ...
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... Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2007. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com ISP1562 All rights reserved. Date of release: 1 March 2007 Document identifier: ISP1562_2 ...