PIC16F690-I/SO Microchip Technology, PIC16F690-I/SO Datasheet - Page 158

• Manufacturer Part Number: PIC16F690-I/SO
• Description: IC PIC MCU FLASH 4KX14 20SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F690-I/SO

• Program Memory Type: FLASH
• Program Memory Size: 7KB (4K x 14)
• Package / Case: 20-SOIC (7.5mm Width)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 18
• Eeprom Size: 256 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: I2C/SPI/SSP/EUSART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 17
• Number Of Timers: 3
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163014, DM164120-1, DM163029
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12-ch x 10-bit
• Data Rom Size: 256 B
• A/d Bit Size: 10 bit
• A/d Channels Available: 12
• Height: 2.31 mm
• Length: 12.8 mm
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.5 V
• Width: 7.49 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT20SO1-1 - SOCKET TRANS ICE 20DIP TO 20SOICPIC16F690DM-PCTLHS - BOARD DEMO PICTAIL HUMIDITY SNSRAC162061 - HEADER INTRFC MPLAB ICD2 20PINAC164039 - MODULE SKT PROMATE II 20DIP/SOIC
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC16F631/677/685/687/689/690
12.1.2.8
1.
2.
3.
4.
5.
6.
7.
8.
9.
FIGURE 12-5:
DS41262C-page 156
Initialize the SPBRGH, SPBRG register pair and
the BRGH and BRG16 bits to achieve the
desired baud rate (see Section 12.3 “EUSART
Baud Rate Generator (BRG)”).
Enable the serial port by setting the SPEN bit.
The SYNC bit must be clear for asynchronous
operation.
If interrupts are desired, set the RCIE interrupt
enable bit and set the GIE and PEIE bits of the
INTCON register.
If 9-bit reception is desired, set the RX9 bit.
Enable reception by setting the CREN bit.
The RCIF interrupt flag bit will be set when a
character is transferred from the receive shift
register to the receive buffer. An interrupt will be
generated if the RCIE interrupt enable bit was
also set.
Read the RCSTA register to get the error flags
and, if 9-bit data reception is enabled, the ninth
data bit.
Get the received 8 Least Significant data bits
from the receive buffer by reading the RCREG
register.
If an overrun occurred, clear the OERR flag by
clearing the CREN receiver enable bit.
Note:
RX/DT pin
Rcv Shift
Reg
Rcv Buffer Reg
Read Rcv
Buffer Reg
RCREG
RCIF
(Interrupt Flag)
OERR bit
CREN
RCIDL
Asynchronous Reception Set-up:
This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word,
causing the OERR (overrun) bit to be set.
Start
ASYNCHRONOUS RECEPTION
bit
bit 0
bit 1
bit 7/8
Preliminary
Stop
bit
Word 1
RCREG
Start
bit
bit 0
12.1.2.9
This mode would typically be used in RS-485 systems.
To set up an Asynchronous Reception with Address
Detect Enable:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. If an overrun occurred, clear the OERR flag by
11. If the device has been addressed, clear the
Initialize the SPBRGH, SPBRG register pair and
the BRGH and BRG16 bits to achieve the
desired baud rate (see Section 12.3 “EUSART
Baud Rate Generator (BRG)”).
Enable the serial port by setting the SPEN bit.
The SYNC bit must be clear for asynchronous
operation.
If interrupts are desired, set the RCIE interrupt
enable bit and set the GIE and PEIE bits of the
INTCON register.
Enable 9-bit reception by setting the RX9 bit.
Enable address detection by setting the ADDEN
bit.
Enable reception by setting the CREN bit.
The RCIF interrupt flag bit will be set when a
character with the ninth bit set is transferred
from the receive shift register to the receive
buffer. An interrupt will be generated if the RCIE
interrupt enable bit was also set.
Read the RCSTA register to get the error flags.
The ninth data bit will always be set.
Get the received 8 Least Significant data bits
from the receive buffer by reading the RCREG
register. Software determines if this is the
device’s address.
clearing the CREN receiver enable bit.
ADDEN bit to allow all received data into the
receive buffer and generate interrupts.
bit 7/8 Stop
Word 2
RCREG
9-bit Address Detection Mode Set-up
bit
Start
© 2006 Microchip Technology Inc.
bit
bit 7/8
Stop
bit