PIC16C64A-04/P Microchip Technology, PIC16C64A-04/P Datasheet - Page 74

• Manufacturer Part Number: PIC16C64A-04/P
• Description: IC MCU OTP 2KX14 PWM 40DIP
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16C64A-04/P

• Core Size: 8-Bit
• Program Memory Size: 3.5KB (2K x 14)
• Core Processor: PIC
• Speed: 4MHz
• Connectivity: I²C, SPI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Type: OTP
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Controller Family/series: PIC16C
• No. Of I/o's: 33
• Ram Memory Size: 128Byte
• Cpu Speed: 4MHz
• No. Of Timers: 3
• No. Of Pwm Channels: 1
• Embedded Interface Type: I2C, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 444-1001 - DEMO BOARD FOR PICMICRO MCU
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: PIC16C64A-04/PR; PIC16C64A-04/PR

PIC16C6X
8.5
CCP2 is implemented on the PIC16C63/R63/65/65A/
R65/66/67 only.
If CCP1 or CCP2 module is configured in Compare
mode
(CCPxM3:CCPxM0 = 1011), this signal will reset
Timer1.
Timer1 must be configured for either timer or synchro-
nized counter mode to take advantage of this feature.
If the Timer1 is running in asynchronous counter mode,
this reset operation may not work.
In the event that a write to Timer1 coincides with a spe-
cial event trigger from CCP1 or CCP2, the write will
take precedence.
In this mode of operation, the CCPRxH:CCPRxL regis-
ters pair effectively becomes the period register for the
Timer1 module.
TABLE 8-2:
DS30234D-page 74
Applicable Devices
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
Address
0Bh,8Bh
10Bh,18Bh
0Ch
8Ch
0Eh
0Fh
10h
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the Timer1 module.
Note 1: The USART is implemented on the PIC16C63/R63/65/65A/R65/66/67 only.
Note:
2: Bits PSPIE and PSPIF are reserved on the PIC16C62/62A/R62/63/R63/66, always maintain these bits clear.
3: PIR1<6> and PIE1<6> are reserved, always maintain these bits clear.
to
Resetting Timer1 using a CCP Trigger
Output
The “special event trigger” from the
CCP1and CCP2 modules will not set inter-
rupt flag bit TMR1IF(PIR1<0>).
INTCON
Name
PIR1
PIE1
TMR1L
TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1 register
T1CON
generate
REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER
Holding register for the Least Significant Byte of the 16-bit TMR1 register
PSPIF
PSPIE
Bit 7
GIE
—
a
(2)
(2)
“special
PEIE
Bit 6
(3)
(3)
—
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
RCIE
RCIF
Bit 5
T0IE
event
(1)
(1)
TXIE
TXIF
trigger”
INTE
Bit 4
(1)
(1)
SSPIF
SSPIE
RBIE
Bit 3
8.6
The TMR1H and TMR1L registers are not reset to 00h
on a POR or any other reset except by the CCP1 or
CCP2 special event trigger.
The T1CON register is reset to 00h on a Power-on
Reset or a Brown-out Reset, which shuts off the timer
and leaves a 1:1 prescaler. In all other resets, the reg-
ister is unaffected.
8.7
The prescaler counter is cleared on writes to the
TMR1H or TMR1L registers.
Applicable Devices
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
Applicable Devices
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
CCP1IF TMR2IF
CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
Bit 2
T0IF
Resetting of TMR1 Register Pair
(TMR1H:TMR1L)
Timer1 Prescaler
INTF
Bit 1
TMR1IF 0000 0000 0000 0000
RBIF
Bit 0
1997 Microchip Technology Inc.
0000 000x 0000 000u
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
Value on:
POR,
BOR
Value on
all other
resets