ST92F150CV1TB STMicroelectronics, ST92F150CV1TB Datasheet - Page 114

• Manufacturer Part Number: ST92F150CV1TB
• Description: MCU 8BIT 128K FLASH 100TQFP
• Manufacturer: STMicroelectronics
• Series: ST9r

Specifications of ST92F150CV1TB

• Core Processor: ST9
• Core Size: 8/16-Bit
• Speed: 24MHz
• Connectivity: CAN, EBI/EMI, I²C, LIN, SCI, SPI
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 77
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 100-TQFP, 100-VQFP
• Processor Series: ST92F15x
• Core: ST9
• Data Bus Width: 8 bit, 16 bit
• Data Ram Size: 6 KB
• Interface Type: CAN, I2C, SCI, SPI
• Maximum Clock Frequency: 24 MHz
• Number Of Programmable I/os: 80
• Number Of Timers: 5 x 16 bit
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST92F150-EPB
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16 bit x 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-4883

ST92F124/F150/F250 - INTERRUPTS
WAKE-UP / INTERRUPT LINES MANAGEMENT UNIT (Cont’d)
5.12.3 Functional Description
5.12.3.1 Interrupt Mode
To configure the 16 wake-up lines as interrupt
sources, use the following procedure:
1. Configure the mask bits of the 16 wake-up lines
2. Configure the triggering edge registers of the
3. Set bit 7 of EIMR (R244 Page 0) and EITR
4. Reset the WKUP-INT bit in the WUCTRL regis-
5. Set the ID1S bit in the WUCTRL register to
5.12.3.2 Wake-up Mode Selection
To configure the 16 lines as wake-up sources, use
the following procedure:
1. Configure the mask bits of the 16 wake-up lines
2. Configure the triggering edge registers of the
3. Set, as for Interrupt Mode selection, bit 7 of
4. Since the RCCU can generate an interrupt
5. Set the WKUP-INT bit in the WUCTRL register
6. Set the ID1S bit in the WUCTRL register to
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9
(WUMRL, WUMRH)
wake-up lines (WUTRL, WUTRH)
(R242 Page 0) registers of the CPU: so an
interrupt coming from one of the 16 lines can be
correctly acknowledged
ter to disable Wake-up Mode
enable the 16 wake-up lines as external inter-
rupt source lines.
(WUMRL, WUMRH).
wake-up lines (WUTRL, WUTRH).
EIMR and EITR registers only if an interrupt
routine is to be executed after a wake-up event.
Otherwise, if the wake-up event only restarts
the execution of the code from where it was
stopped, the INTD1 interrupt channel must be
masked.
request when exiting from STOP mode, take
care to mask it even if the wake-up event is
only to restart code execution.
to select Wake-up Mode
enable the 16 wake-up lines as external inter-
rupt source lines. This is not mandatory if the
7. Write the sequence 1,0,1 to the STOP bit of the
To detect if STOP Mode was entered or not, im-
mediately after the STOP bit setting sequence,
poll the RCCU EX_STP bit (R242.7, Page 55) and
the STOP bit itself.
5.12.3.3 STOP Mode Entry Conditions
Assuming the ST9 is in Run mode: during the
STOP bit setting sequence the following cases
may occur:
Case 1: NMI = 0, wrong STOP bit setting se-
quence
This can happen if an Interrupt/DMA request is ac-
knowledged during the STOP bit setting se-
quence. In this case polling the STOP and
EX_STP bits will give:
STOP = 0, EX_STP = 0
This means that the ST9 did not enter STOP mode
due to a bad STOP bit setting sequence: the user
must retry the sequence.
Case 2: NMI = 0, correct STOP bit setting se-
quence
In this case the ST9 enters STOP mode. There are
two ways to exit STOP mode:
1. A wake-up interrupt (not an NMI interrupt) is
This means that the ST9 entered and exited STOP
mode due to an external wake-up line event.
2. A NMI rising edge woke up the ST9. This
This means that the ST9 entered and exited STOP
mode due to an NMI (rising edge) event. The user
should clear the STOP bit via software.
wake-up event does not require an interrupt
response.
WUCTRL register with three consecutive write
operations. This is the STOP bit setting
sequence.
acknowledged. That implies:
implies:
STOP = 0, EX_STP = 1
STOP = 1, EX_STP = 1