ST92F150CV1TB STMicroelectronics, ST92F150CV1TB Datasheet - Page 365

• Manufacturer Part Number: ST92F150CV1TB
• Description: MCU 8BIT 128K FLASH 100TQFP
• Manufacturer: STMicroelectronics
• Series: ST9r

Specifications of ST92F150CV1TB

• Core Processor: ST9
• Core Size: 8/16-Bit
• Speed: 24MHz
• Connectivity: CAN, EBI/EMI, I²C, LIN, SCI, SPI
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 77
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 100-TQFP, 100-VQFP
• Processor Series: ST92F15x
• Core: ST9
• Data Bus Width: 8 bit, 16 bit
• Data Ram Size: 6 KB
• Interface Type: CAN, I2C, SCI, SPI
• Maximum Clock Frequency: 24 MHz
• Number Of Programmable I/os: 80
• Number Of Timers: 5 x 16 bit
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST92F150-EPB
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16 bit x 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-4883

ANALOG TO DIGITAL CONVERTER (Cont’d)
Figure 158. Application Example: Analog Watchdog used in Motor Speed Control
10.11.4 Interrupts
The ADC provides two interrupt sources:
– End of Conversion
– Analog Watchdog Request
The ADC Interrupt Vector Register (IVR, R255
Page 63) provides hardware generated flags
which indicate the interrupt source, thus allowing
the automatic selection of the correct interrupt
service routine.
The ADC Interrupt vector should be programmed
by the user to point to the first memory location in
Request
dog Re-
Watch-
Analog
End of
Conv.
quest
X
X
7
7
X
X
X
X
X
X
X
X
X
X
0
1
0
0
0
0
Address
Address
Lower
Upper
Word
Word
10-BIT ANALOG TO DIGITAL CONVERTER (ADC)
the Interrupt Vector table containing the base ad-
dress of the four byte area of the interrupt vector
table in which the address of the ADC interrupt
service routines are stored.
The Analog Watchdog Interrupt Pending bit (AWD,
ICR.6) is automatically set by hardware whenever
any of the two guarded analog inputs go out of
range. The Compare Result Register (CRR) tracks
the analog inputs which exceed their programmed
thresholds.
When two requests occur simultaneously, the An-
alog Watchdog Request has priority over the End
of Conversion request, which is held pending.
The Analog Watchdog Request requires the user
to poll the Compare Result Register (CRR) to de-
termine which of the four thresholds has been ex-
ceeded. The threshold status bits are set to flag an
out of range condition, and are automatically reset
by hardware after a software reset of the Analog
Watchdog Request flag in the ICR Register. The
interrupt pending flags, ECV and AWD, should be
reset by the user within the interrupt service rou-
tine. Setting either of these two bits by software
will cause an interrupt request to be generated.
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