ST92F150CV1TB STMicroelectronics, ST92F150CV1TB Datasheet - Page 343

• Manufacturer Part Number: ST92F150CV1TB
• Description: MCU 8BIT 128K FLASH 100TQFP
• Manufacturer: STMicroelectronics
• Series: ST9r

Specifications of ST92F150CV1TB

• Core Processor: ST9
• Core Size: 8/16-Bit
• Speed: 24MHz
• Connectivity: CAN, EBI/EMI, I²C, LIN, SCI, SPI
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 77
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 100-TQFP, 100-VQFP
• Processor Series: ST92F15x
• Core: ST9
• Data Bus Width: 8 bit, 16 bit
• Data Ram Size: 6 KB
• Interface Type: CAN, I2C, SCI, SPI
• Maximum Clock Frequency: 24 MHz
• Number Of Programmable I/os: 80
• Number Of Timers: 5 x 16 bit
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST92F150-EPB
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16 bit x 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-4883

CONTROLLER AREA NETWORK (Cont’d)
10.10.8 Register Description
10.10.8.1 Control and Status Registers
CAN MASTER CONTROL REGISTER (CMCR)
Reset Value: 0000 0010 (02h)
Bit 7 = TTCM Time Triggered Communication
Mode
- Read/Set/Clear
0: Time Triggered Communication mode disabled.
1: Time Triggered Communication mode enabled
Note: For more information on Time Triggered
Communication mode, please refer to
10.10.5.2 Time Triggered Communication
Bit 6 = ABOM Automatic Bus-Off Management
- Read/Set/Clear
This bit controls the behaviour of the CAN hard-
ware on leaving the Bus-Off state.
0: The Bus-Off state is left on software request,
1: The Bus-Off state is left automatically by hard-
For detailed information on the Bus-Off state
please refer to
ment.
Bit 5 = AWUM Automatic Wake-Up Mode
- Read/Set/Clear
This bit controls the behaviour of the CAN hard-
ware on message reception during sleep mode.
0: The sleep mode is left on software request by
1: The sleep mode is left automatically by hard-
Bit 4 = NART No Automatic Retransmission
0: The CAN hardware will automatically retransmit
TTCM ABOM AWUM NART RFLM TXFP SLEEP INRQ
once 128 x 11 recessive bits have been moni-
tored and the software has first set and cleared
the INRQ bit of the CMCR register.
ware once 128 x 11 recessive bits have been
monitored.
clearing the SLEEP bit of the CMCR register.
ware on CAN message detection. The SLEEP
bit of the CMCR register and the SLAK bit of the
CMSR register are cleared by hardware.
- Read/Set/Clear
the message until it has been successfully
transmitted according to the CAN standard.
7
Section 10.10.5.6 Error Manage-
Section
Mode.
0
CONTROLLER AREA NETWORK (bxCAN)
1: A message will be transmitted only once, inde-
Bit 3 = RFLM Receive FIFO Locked Mode
- Read/Set/Clear
0: Receive FIFO not locked on overrun. Once a re-
1: Receive FIFO locked against overrun. Once a
Bit 2 = TXFP Transmit FIFO Priority
- Read/Set/Clear
This bit controls the transmission order when sev-
eral mailboxes are pending at the same time.
0: Priority driven by the identifier of the message
1: Priority driven by the request order (chronologi-
Bit 1 = SLEEP Sleep Mode Request
- Read/Set/Clear
This bit is set by software to request the CAN hard-
ware to enter the sleep mode. Sleep mode will be
entered as soon as the current CAN activity (trans-
mission or reception of a CAN frame) has been
completed.
This bit is cleared by software to exit sleep mode.
This bit is cleared by hardware when the AWUM
bit is set and a SOF bit is detected on the CAN Rx
signal.
Bit 0 = INRQ Initialization Request
- Read/Set/Clear
The software clears this bit to switch the hardware
into normal mode. Once 11 consecutive recessive
bits have been monitored on the Rx signal the
CAN hardware is synchronized and ready for
transmission and reception. Hardware signals this
event by clearing the INAK bit if the CMSR regis-
ter.
Software sets this bit to request the CAN hardware
to enter initialization mode. Once software has set
the INRQ bit, the CAN hardware waits until the
current CAN activity (transmission or reception) is
completed before entering the initialization mode.
Hardware signals this event by setting the INAK bit
in the CMSR register.
pendently of the transmission result (successful,
error or arbitration lost).
ceive FIFO is full the next incoming message
will overwrite the previous one.
receive FIFO is full the next incoming message
will be discarded.
cally)
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