ST10R167-Q3 STMicroelectronics, ST10R167-Q3 Datasheet - Page 59

IC MCU 16BIT ROMLESS 144-PQFP

ST10R167-Q3

Manufacturer Part Number
ST10R167-Q3
Description
IC MCU 16BIT ROMLESS 144-PQFP
Manufacturer
STMicroelectronics
Series
ST10r
Datasheet

Specifications of ST10R167-Q3

Core Processor
ST10
Core Size
16-Bit
Speed
25MHz
Connectivity
CAN, EBI/EMI, SSC, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
111
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
144-QFP
Processor Series
ST10R1x
Core
ST10
Data Bus Width
16 bit
Program Memory Size
32 KB
Data Ram Size
4 KB
Interface Type
CAN/SSC/USART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
111
Number Of Timers
5
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
16-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
497-2043

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XX - ELECTRICAL CHARACTERISTICS (continued)
Figure 22 : CLKOUT and READY
Notes 1. Cycle as programmed, including MCTC waitstates (Example shows 0 MCTC WS).
2. The leading edge of the respective command depends on RW-delay.
3. READY sampled HIGH at this sampling point generates a READY controlled wait state, READY sampled LOW at this sampling
point terminates the currently running bus cycle.
4. READY may be deactivated in response to the trailing (rising) edge of the corresponding command (RD or WR).
5. If the Asynchronous READY signal does not fulfill the indicated setup and hold times with respect to CLKOUT (e.g. because
CLKOUT is not enabled), it must fulfill t
to the command (see Note 4)).
6. Multiplexed bus modes have a MUX waitstate added after a bus cycle, and an additional MTTC waitstate may be inserted here.
For a multiplexed bus with MTTC waitstate this delay is 2 CLKOUT cycles, for a demultiplexed bus without MTTC waitstate this delay
is zero.
7. The next external bus cycle may start here.
Command
READY
READY
CLKOUT
RD, WR
Async
Sync
ALE
t
t
58
32
3)
Running cycle 1)
t
t
t
59
30
34
37
2)
in order to be safely synchronized. This is guaranteed, if READY is removed in response
t
t
33
31
t
t
35
58
5)
3)
t
37
3)
t
t
36
59
t
29
t
35
waitstate
READY
3)
t
36
MUX/Tristate 6)
t
60 4)
6)
7)
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