PIC18F2221-I/ML Microchip Technology, PIC18F2221-I/ML Datasheet - Page 306
![IC PIC MCU FLASH 2KX16 28QFN](/photos/6/81/68120/150-28-qfn_sml.jpg)
PIC18F2221-I/ML
Manufacturer Part Number
PIC18F2221-I/ML
Description
IC PIC MCU FLASH 2KX16 28QFN
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC18F2221-ISO.pdf
(402 pages)
2.PIC18F2221-ISO.pdf
(8 pages)
3.PIC18F2221-ISO.pdf
(30 pages)
4.PIC18F2221-ISO.pdf
(46 pages)
5.PIC18F2321-IML.pdf
(396 pages)
Specifications of PIC18F2221-I/ML
Core Size
8-Bit
Program Memory Size
4KB (2K x 16)
Core Processor
PIC
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
25
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Controller Family/series
PIC18
No. Of I/o's
25
Eeprom Memory Size
256Byte
Ram Memory Size
512Byte
Cpu Speed
40MHz
No. Of Timers
4
Package
28QFN EP
Device Core
PIC
Family Name
PIC18
Maximum Speed
40 MHz
Operating Supply Voltage
5 V
Data Bus Width
8 Bit
Number Of Programmable I/os
25
Interface Type
I2C/SPI/USART
On-chip Adc
10-chx10-bit
Number Of Timers
4
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT28QFN4 - SOCKET TRANS ICE 28QFN W/CABLEAC164322 - MODULE SOCKET MPLAB PM3 28/44QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC18F2221-I/ML
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- PIC18F2221-ISO PDF datasheet
- PIC18F2221-ISO PDF datasheet #2
- PIC18F2221-ISO PDF datasheet #3
- PIC18F2221-ISO PDF datasheet #4
- PIC18F2321-IML PDF datasheet #5
- Current page: 306 of 396
- Download datasheet (7Mb)
PIC18F4321 FAMILY
RETFIE
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
DS39689E-page 304
Q Cycle Activity:
After Interrupt
operation
Decode
PC
W
BSR
STATUS
GIE/GIEH, PEIE/GIEL
Q1
No
operation
operation
Return from Interrupt
RETFIE {s}
s ∈ [0,1]
(TOS) → PC,
1 → GIE/GIEH or PEIE/GIEL,
if s = 1
(WS) → W,
(STATUSS) → STATUS,
(BSRS) → BSR,
PCLATU, PCLATH are unchanged
GIE/GIEH, PEIE/GIEL.
Return from interrupt. Stack is popped
and Top-of-Stack (TOS) is loaded into
the PC. Interrupts are enabled by
setting either the high or low priority
global interrupt enable bit. If ‘s’ = 1, the
contents of the shadow registers, WS,
STATUSS and BSRS, are loaded into
their corresponding registers, W,
STATUS and BSR. If ‘s’ = 0, no update
of these registers occurs (default).
1
2
RETFIE
0000
Q2
No
No
1
0000
operation
operation
=
=
=
=
=
Q3
No
No
TOS
WS
BSRS
STATUSS
1
0001
Set GIEH or
from stack
operation
POP PC
GIEL
Q4
No
000s
Preliminary
RETLW
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
TABLE
Q Cycle Activity:
:
:
:
CALL TABLE ; W contains table
ADDWF PCL
RETLW k0
RETLW k1
RETLW kn
Before Instruction
After Instruction
operation
Decode
W
W
Q1
No
; offset value
; W now has
; table value
; W = offset
; Begin table
;
; End of table
=
=
operation
Return Literal to W
RETLW k
0 ≤ k ≤ 255
k → W,
(TOS) → PC,
PCLATU, PCLATH are unchanged
None
W is loaded with the eight-bit literal ‘k’.
The program counter is loaded from the
top of the stack (the return address).
The high address latch (PCLATH)
remains unchanged.
1
2
literal ‘k’
Read
0000
Q2
No
07h
value of kn
© 2007 Microchip Technology Inc.
1100
operation
Process
Data
Q3
No
kkkk
from stack,
Write to W
operation
POP PC
Q4
No
kkkk
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