DSPIC30F6014A-20E/PT Microchip Technology, DSPIC30F6014A-20E/PT Datasheet - Page 57

• Manufacturer Part Number: DSPIC30F6014A-20E/PT
• Description: IC DSPIC MCU/DSP 144K 80TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F6014A-20E/PT

• Program Memory Type: FLASH
• Program Memory Size: 144KB (48K x 24)
• Package / Case: 80-TFQFP
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: AC'97, Brown-out Detect/Reset, I²S, LVD, POR, PWM, WDT
• Number Of I /o: 68
• Eeprom Size: 4K x 8
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Product: DSCs
• Data Bus Width: 16 bit
• Processor Series: DSPIC30F
• Core: dsPIC
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 68
• Data Ram Size: 8 KB
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE4000, DM240002, DM330011
• Minimum Operating Temperature: - 40 C
• Package: 80TQFP
• Device Core: dsPIC
• Family Name: dsPIC30
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 3.3|5 V
• Interface Type: CAN/I2C/SPI/UART
• On-chip Adc: 16-chx12-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DM300024 - KIT DEMO DSPICDEM 1.1XLT80PT3 - SOCKET TRAN ICE 80MQFP/TQFPAC164320 - MODULE SKT MPLAB PM3 80TQFPDM300004-2 - BOARD DEMO DSPICDEM.NET 2DM300004-1 - BOARD DEMO DSPICDEM.NET 1AC30F007 - MODULE SKT FOR DSPIC30F 80TQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

7.0
The Data EEPROM Memory is readable and writable
during normal operation over the entire V
data EEPROM memory is directly mapped in the
program memory address space.
The four SFRs used to read and write the program
Flash memory are used to access data EEPROM
memory, as well. As described in
Registers”, these registers are:
• NVMCON
• NVMADR
• NVMADRU
• NVMKEY
The EEPROM data memory allows read and write of
single words and 16-word blocks. When interfacing to
data memory, NVMADR in conjunction with the
NVMADRU register are used to address the EEPROM
location being accessed. TBLRDL and TBLWTL
instructions are used to read and write data EEPROM.
The dsPIC30F devices have up to 8 Kbytes (4K
words) of data EEPROM with an address range from
0x7FF000 to 0x7FFFFE.
A word write operation should be preceded by an erase
of the corresponding memory location(s). The write typ-
ically requires 2 ms to complete but the write time will
vary with voltage and temperature.
© 2011 Microchip Technology Inc.
Note:
DATA EEPROM MEMORY
This data sheet summarizes features of
this group of dsPIC30F devices and is not
intended to be a complete reference
source. For more information on the CPU,
peripherals, register descriptions and
general device functionality, refer to the
“dsPIC30F Family Reference Manual”
(DS70046). For more information on the
device instruction set and programming,
refer to the “16-bit MCU and DSC
Programmer’s
(DS70157).
dsPIC30F6011A/6012A/6013A/6014A
Reference
Section 6.5 “Control
DD
range. The
Manual”
A program or erase operation on the data EEPROM
does not stop the instruction flow. The user is respon-
sible for waiting for the appropriate duration of time
before initiating another data EEPROM write/erase
operation. Attempting to read the data EEPROM while
a programming or erase operation is in progress results
in unspecified data.
Control bit WR initiates write operations similar to pro-
gram Flash writes. This bit cannot be cleared, only set,
in software. They are cleared in hardware at the com-
pletion of the write operation. The inability to clear the
WR bit in software prevents the accidental or
premature termination of a write operation.
The WREN bit, when set, will allow a write operation.
On power-up, the WREN bit is clear. The WRERR bit is
set when a write operation is interrupted by a MCLR
Reset or a WDT Time-out Reset during normal opera-
tion. In these situations, following Reset, the user can
check the WRERR bit and rewrite the location. The
address register NVMADR remains unchanged.
7.1
A TBLRD instruction reads a word at the current pro-
gram word address. This example uses W0 as a
pointer to data EEPROM. The result is placed in
register W4 as shown in
EXAMPLE 7-1:
MOV
MOV
MOV
TBLRDL [ W0 ], W4
Note:
Reading the Data EEPROM
#LOW_ADDR_WORD,W0
#HIGH_ADDR_WORD,W1
W1
Interrupt flag bit NVMIF in the IFS0 regis-
ter is set when write is complete. It must
be cleared in software.
,
TBLPAG
DATA EEPROM READ
Example
; Init Pointer
; read data EEPROM
7-1.
DS70143E-page 57