ST7FLI49MK1T6 STMicroelectronics, ST7FLI49MK1T6 Datasheet - Page 64

MCU 8BIT SGL VOLT FLASH 32-LQFP

ST7FLI49MK1T6

Manufacturer Part Number
ST7FLI49MK1T6
Description
MCU 8BIT SGL VOLT FLASH 32-LQFP
Manufacturer
STMicroelectronics
Series
ST7r
Datasheet

Specifications of ST7FLI49MK1T6

Core Processor
ST7
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
24
Program Memory Size
4KB (4K x 8)
Program Memory Type
FLASH
Eeprom Size
128 x 8
Ram Size
384 x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-LQFP
Processor Series
ST7FLI4x
Core
ST7
Data Bus Width
8 bit
Data Ram Size
384 B
Interface Type
I2C
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
24
Number Of Timers
5
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 10 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Power saving modes
64/188
As soon as Halt mode is entered, and if the AWUEN bit has been set in the AWUCSR
register, the AWU RC oscillator provides a clock signal (f
a fixed divider and a programmable prescaler controlled by the AWUPR register. The output
of this prescaler provides the delay time. When the delay has elapsed, the following actions
are performed:
After this start-up delay, the CPU resumes operation by servicing the AWUFH interrupt. The
AWU flag and its associated interrupt are cleared by software reading the AWUCSR
register.
To compensate for any frequency dispersion of the AWU RC oscillator, it can be calibrated
by measuring the clock frequency f
Measurement mode is enabled by setting the AWUM bit in the AWUCSR register in Run
mode. This connects f
f
Similarities with Halt mode
The following AWUFH mode behavior is the same as normal Halt mode:
Figure 32. AWUF Halt timing diagram
AWU_RC
AWUFH interrupt
f
f
AWU_RC
CPU
the AWUF flag is set by hardware,
an interrupt wakes up the MCU from Halt mode,
the main oscillator is immediately turned on and the 256 CPU cycle delay is used to
stabilize it.
The MCU can exit AWUFH mode by means of any interrupt with exit from Halt
capability or a reset (see
When entering AWUFH mode, the I bit in the CC register is forced to 0 to enable
interrupts. Therefore, if an interrupt is pending, the MCU wakes up immediately.
In AWUFH mode, the main oscillator is turned off causing all internal processing to be
stopped, including the operation of the on-chip peripherals. None of the peripherals are
clocked except those which get their clock supply from another clock generator (such
as an external or auxiliary oscillator like the AWU oscillator).
The compatibility of watchdog operation with AWUFH mode is configured by the
WDGHALT option bit in the option byte. Depending on this setting, the HALT instruction
when executed while the watchdog system is enabled, can generate a watchdog reset.
to be measured using the main oscillator clock as a reference timebase.
RUN MODE
AWU_RC
Section 9.4: Active-halt and Halt
to the input capture of the 8-bit Lite timer, allowing the
Doc ID 13562 Rev 3
HALT MODE
AWU_RC
t
AWU
and then calculating the right prescaler value.
256 t
AWU_RC
CPU
modes).
). Its frequency is divided by
RUN MODE
ST7LITE49M
Clear
by software

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