Z8F012ASB020SG Zilog, Z8F012ASB020SG Datasheet - Page 45

• Manufacturer Part Number: Z8F012ASB020SG
• Description: IC ENCORE XP MCU FLASH 1K 8SOIC
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F012ASB020SG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: IrDA, UART/USART
• Peripherals: Brown-out Detect/Reset, LED, LVD, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 6
• Program Memory Size: 1KB (1K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 16 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 8-SOIC (3.9mm Width)
• Processor Series: Z8F012Ax
• Core: eZ8
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 6
• Number Of Timers: 2
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: Z8F04A08100KITG, Z8F04A28100KITG, ZENETSC0100ZACG, ZENETSC0100ZACG, ZUSBOPTSC01ZACG, ZUSBSC00100ZAC, ZUSBSC00100ZACG
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 4 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4039; Z8F012ASB020SG

HALT Mode
Peripheral-Level Power Control
Power Control Register Definitions
PS022825-0908
Power Control Register 0
Executing the eZ8 CPU’s HALT instruction places the device into HALT mode, which
powers down the CPU but leaves all other peripherals active. In HALT mode, the
operating characteristics are:
The eZ8 CPU can be brought out of HALT mode by any of the following operations:
To minimize current in HALT mode, all GPIO pins that are configured as inputs must be
driven to one of the supply rails (V
In addition to the STOP and HALT modes, it is possible to disable each peripheral on each
of the Z8 Encore! XP F082A Series devices. Disabling a given peripheral minimizes its
power consumption.
The following sections define the Power Control registers.
Each bit of the following registers disables a peripheral block, either by gating its system
clock input or by removing power from the block. The default state of the low-power
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Primary oscillator is enabled and continues to operate.
System clock is enabled and continues to operate.
eZ8 CPU is stopped.
Program counter (PC) stops incrementing.
Watchdog Timer’s internal RC oscillator continues to operate.
If enabled, the Watchdog Timer continues to operate.
All other on-chip peripherals continue to operate, if enabled.
Interrupt
Watchdog Timer time-out (interrupt or reset)
Power-On Reset
Voltage Brownout reset
External RESET pin assertion
CC
or GND).
Z8 Encore! XP
Product Specification
®
Low-Power Modes
F082A Series
34