ST72F621L4M1 STMicroelectronics, ST72F621L4M1 Datasheet
ST72F621L4M1
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ST72F621L4M1 Summary of contents
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Low speed USB 8-bit MCU with 3 endpoints, Flash or ROM memory, LVD, WDG, 10-bit ADC, 2 timers, SCI, SPI Features Memories ■ – Kbyte Program memory (ROM or Dual voltage FLASH) with read-write protection – In-Application ...
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INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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A/D CONVERTER (ADC ...
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ST7262xxx 1 INTRODUCTION The ST7262 and ST72F62 devices are members of the ST7 microcontroller family designed for USB applications. All devices are based on a common industry- standard 8-bit core, featuring an enhanced instruc- tion set. The ST7262 devices are ...
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PIN DESCRIPTION Figure 2. 44-pin LQFP and 42-Pin SDIP Package Pinouts MOSI / PC6 IT12 / MISO / PC5 IT11 / SS / PC4 IT10 / SCK / PC3 IT9 / PC2 OSCOUT MOSI / PC6 IT12 / MISO ...
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ST7262xxx PIN DESCRIPTION (Cont’d) Figure 3. 34-Pin SO and 32-Pin SDIP Package Pinouts IT10 / SCK / PC3 IT8 / PWM1 / PB7 (HS) ICCDATA / IT7 / PWM0 / PB6 (HS) ICCCLK / IT6 /ARTIC2 / PB5 (HS) IT5 ...
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Figure 4. 20-pin SO20 Package Pinout IT3 / AIN2 / PA2 IT2 / AIN1 / PA1 USBOE/ IT1 / AIN0/ PA0 Figure 5. 20-pin DIP20 Package Pinout IT5 / ARTIC1 / PB4 (HS) ARTCLK / PB3 (HS) MCO / PB0 ...
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ST7262xxx PIN DESCRIPTION (Cont’d) Legend / Abbreviations: Type Input Output Supply Input level Dedicated analog input Input level CMOS 0. CMOS 0.3V T Output level High ...
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Pin n° Pin Name PB6/PWM0/IT7 ICCDATA PB5/ARTIC2/IT6 ICCCLK PB4/ARTIC1/IT5 PB3/ARTCLK ...
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ST7262xxx Pin n° Pin Name PD3 PD2 Note 1: Peripheral not present on all devices. Refer to 2.1 PCB LAYOUT RECOMMENDATION In the case of DIP20 devices the ...
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REGISTER & MEMORY MAP As shown in the Figure 7, the MCU is capable of addressing 64K bytes of memories and I/O regis- ters. The available memory locations consist of 64 bytes of register locations, 768 bytes of RAM ...
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ST7262xxx Table 2. Hardware Register Map Register Address Block Label 0000h PADR Port A 0001h PADDR 0002h PBDR Port B 0003h PBDDR 0004h PCDR Port C 0005h PCDDR 0006h PDDR Port D 0007h PDDDR 0008h ITRFRE1 0009h MISC 000Ah ADCDRMSB ...
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Register Address Block Label 0025h USBPIDR 0026h USBDMAR 0027h USBIDR 0028h USBISTR 0029h USBIMR 002Ah USBCTLR 002Bh USB USBDADDR 002Ch USBEP0RA 002Dh USBEP0RB 002Eh USBEP1RA 002Fh USBEP1RB 0030h USBEP2RA 0031h USBEP2RB 0032h to 0035h 0036h TBUCV TBU 0037h TBUCSR 0038h ...
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ST7262xxx 4 FLASH PROGRAM MEMORY 4.1 INTRODUCTION The ST7 dual voltage High Density Flash (HDFlash non-volatile memory that can be electrically erased as a single block or by individu- al sectors and programmed on a Byte-by-Byte ba- sis ...
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FLASH PROGRAM MEMORY (Cont’d) 4.4 ICC INTERFACE ICC (In-Circuit Communication) needs a minimum of four and up to six pins to be connected to the programming tool (see Figure – RESET: device reset – device power supply ground ...
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... Flash memory programming can be fully custom- ized (number of bytes to program, program loca- tions, or selection serial communication interface for downloading). When using an STMicroelectronics or third-party programming tool that supports ICP and the spe- cific microcontroller device, the user needs only to implement the ICP hardware interface on the ap- ...
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CENTRAL PROCESSING UNIT 5.1 INTRODUCTION This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8-bit data manipulation. 5.2 MAIN FEATURES Enable executing 63 basic instructions ■ Fast 8-bit by 8-bit multiply ■ 17 main ...
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ST7262xxx CENTRAL PROCESSING UNIT (Cont’d) Condition Code Register (CC) Read/Write Reset Value: 111x1xxx The 8-bit Condition Code register contains the in- terrupt masks and four flags representative of the result of the instruction just ...
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CPU REGISTERS (Cont’d) STACK POINTER (SP) Read/Write Reset Value: 017Fh SP6 SP5 SP4 SP3 The Stack Pointer is a 16-bit register which is al- ways pointing to the next free location in ...
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ST7262xxx 6 CLOCKS AND RESET 6.1 CLOCK SYSTEM 6.1.1 General Description The MCU accepts either a Crystal or Ceramic res- onator external clock signal to drive the in- ternal oscillator. The internal clock (f rived from the external ...
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Figure 14. Clock block diagram 6.2 RESET The Reset procedure is used to provide an orderly software start- exit low power modes. Three reset modes are provided: a low voltage re- set, a watchdog reset and an external ...
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ST7262xxx Figure 16. Low Voltage Reset V IT RESET Note: Typical hysteresis (V IT+ Figure 17. Temporization Timing Diagram after an internal Reset V DD Addresses Figure 18. Reset Timing Diagram t DDR V DD OSCIN t OXOV ...
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Figure 19. Reset Block Diagram V DD RESET Note: The output of the external reset circuit must have an open-drain output to drive the ST7 reset pad. Otherwise the device can be damaged when the ST7 generates an internal reset ...
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ST7262xxx 7 INTERRUPTS 7.1 INTRODUCTION The CPU enhanced interrupt management pro- vides the following features: Hardware interrupts ■ Software interrupt (TRAP) ■ Nested or concurrent interrupt management ■ with flexible interrupt management: – software programmable nesting levels ...
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INTERRUPTS (Cont’d) Servicing Pending Interrupts As several interrupts can be pending at the same time, the interrupt to be taken into account is deter- mined by the following two-step process: – the highest software priority interrupt is serviced, – if ...
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ST7262xxx INTERRUPTS (Cont’d) 7.3 INTERRUPTS AND LOW POWER MODES All interrupts allow the processor to exit the WAIT low power mode. On the contrary, only external and other specified interrupts allow the processor to exit from the HALT modes (see ...
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INTERRUPTS (Cont’d) 7.5 INTERRUPT REGISTER DESCRIPTION CPU CC REGISTER INTERRUPT BITS Read/Write Reset Value: 111x 1010 (xAh Bit I1, I0 Software Interrupt Priority These two bits indicate the current interrupt soft- ...
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ST7262xxx INTERRUPTS (Cont’d) INTERRUPT REGISTER 1 (ITRFRE1) Address: 0008h - Read/Write Reset Value: 0000 0000 (00h) 7 IT8E IT7E IT6E IT5E IT4E Bit 7:0 = ITiE Interrupt Enable 0: I/O pin free for general purpose I/O 1: ITi external interrupt ...
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INTERRUPTS (Cont’d) Table 6. Interrupt Mapping Source N° Block Reset TRAP software interrupt 0 ICP FLASH Start programming NMI interrupt 1 USB USB End Suspend interrupt 2 Port A external interrupts IT[4:1] 3 I/O Ports Port B external interrupts IT[8:5] ...
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ST7262xxx 8 POWER SAVING MODES 8.1 INTRODUCTION There are three Power Saving modes. Slow Mode is selected by setting the SMS bits in the Miscella- neous register. Wait and Halt modes may be en- tered using the WFI and HALT ...
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POWER SAVING MODES (Cont’d) 8.3 HALT MODE The HALT mode is the MCU lowest power con- sumption mode. The HALT mode is entered by ex- ecuting the HALT instruction. The internal oscilla- tor is then turned off, causing all internal ...
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ST7262xxx 9 I/O PORTS 9.1 INTRODUCTION The I/O ports offer different functional modes: transfer of data through digital inputs and outputs and for specific pins: – Analog signal input (ADC) – Alternate signal input/output for the on-chip pe- ripherals. – ...
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I/O PORTS (Cont’d) Analog Alternate Functions When the pin is used as an ADC input, the I/O must be configured as input. The analog multiplex- er (controlled by the ADC registers) switches the analog voltage present on the selected pin ...
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ST7262xxx I/O PORTS (Cont’d) 9.2.5 Port A Table 9. Port A Description PORT A Input* PA0 floating PA1 floating PA2 floating PA3 floating PA4 floating PA5 floating PA6 floating PA7 floating *Reset State Figure 26. PA[7:0] Configuration ALTERNATE OUTPUT DR ...
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I/O PORTS (Cont’d) 9.2.6 Port B Table 10. Port B Description PORT B Input* PB0 floating PB1 floating PB2 floating PB3 floating PB4 floating PB5 floating PB6 floating PB7 floating *Reset State Figure 27. Port B and Port C [7:2] ...
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ST7262xxx I/O PORTS (Cont’d) 9.2.7 Port C Table 11. Port C Description PORT C Input* PC0 floating PC1 floating PC2 with pull-up PC3 with pull-up PC4 with pull-up PC5 with pull-up PC6 with pull-up PC7 with pull-up *Reset State Figure ...
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I/O PORTS (Cont’d) 9.2.8 Port D Table 12. Port D Description PORT D Input* PD0 with pull-up PD1 with pull-up PD2 with pull-up PD3 with pull-up PD4 with pull-up PD5 with pull-up PD6 with pull-up *Reset State Figure 29. Port ...
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ST7262xxx I/O PORTS (Cont’d) 9.2.9 Register Description DATA REGISTER (DR) Port x Data Register PxDR with Read/Write Reset Value: 0000 0000 (00h Bits 7:0 = D[7:0] Data ...
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I/O PORTS (Cont’d) Table 13. I/O Port Register Map and Reset Values Address Register 7 Label (Hex.) Reset Value 0 of all I/O port registers 0000h PADR MSB 0001h PADDR 0002h PBDR MSB 0003h PBDDR 0004h PCDR MSB 0005h PCDDR ...
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ST7262xxx 9.3 MISCELLANEOUS REGISTER MISCELLANEOUS REGISTER Read Write Reset Value - 0000 0000 (00h SMS1 SMS0 Bits 7:4 = Reserved Bits 3:2 = SMS[1:0] Slow Mode Selection These bits select the Slow Mode frequency (de- ...
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ON-CHIP PERIPHERALS 10.1 WATCHDOG TIMER (WDG) 10.1.1 Introduction The Watchdog timer is used to detect the occur- rence of a software fault, usually generated by ex- ternal interference or by unforeseen logical condi- tions, which causes the application program ...
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ST7262xxx WATCHDOG TIMER (Cont’d) 10.1.4 Software Watchdog Option If Software Watchdog is selected by option byte, the watchdog is disabled following a reset. Once activated it cannot be disabled, except by a reset. The T6 bit can be used to ...
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PWM AUTO-RELOAD TIMER (ART) 10.2.1 Introduction The Pulse Width Modulated Auto-Reload Timer on-chip peripheral consists of an 8-bit auto reload counter with compare/capture capabilities and of a 7-bit prescaler clock source. These resources allow five possible operating modes: – ...
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ST7262xxx PWM AUTO-RELOAD TIMER (Cont’d) 10.2.2 Functional Description Counter The free running 8-bit counter is fed by the output of the prescaler, and is incremented on every ris- ing edge of the clock signal possible to read or ...
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PWM AUTO-RELOAD TIMER (Cont’d) Independent PWM signal generation This mode allows up to two Pulse Width Modulat- ed signals to be generated on the PWMx output pins with minimum core processing overhead. This function is stopped during HALT mode. Each ...
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ST7262xxx Figure 34. PWM Signal from 0% to 100% Duty Cycle f COUNTER COUNTER FDh OCRx=FCh OCRx=FDh OCRx=FEh OCRx=FFh 46/139 ARTARR=FDh FEh FFh FDh FEh Doc ID 6996 Rev 5 FFh FDh FEh t ...
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PWM AUTO-RELOAD TIMER (Cont’d) Output compare and Time base interrupt On overflow, the OVF flag of the ARTCSR register is set and an overflow interrupt request is generat the overflow interrupt enable bit, OIE, in the ARTCSR register, ...
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ST7262xxx PWM AUTO-RELOAD TIMER (Cont’d) Input capture function This mode allows the measurement of external signal pulse widths through ICRx registers. Each input capture can generate an interrupt inde- pendently on a selected input signal transition. This event is flagged ...
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PWM AUTO-RELOAD TIMER (Cont’d) 10.2.3 Register Description CONTROL / STATUS REGISTER (CSR) Read/Write Reset Value: 0000 0000 (00h) 7 EXCL CC2 CC1 CC0 TCE Bit 7 = EXCL External Clock This bit is set and cleared by software. It selects ...
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ST7262xxx PWM AUTO-RELOAD TIMER (Cont’d) PWM CONTROL REGISTER (PWMCR) Read/Write Reset Value: 0000 0000 (00h OE1 OE0 0 Bit 7:6 = Reserved. Bit 5:4 = OE[1:0] PWM Output Enable These bits are set and cleared by software. ...
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PWM AUTO-RELOAD TIMER (Cont’d) INPUT CAPTURE CONTROL / STATUS REGISTER (ARTICCSR) Read/Write (except bits 1:0 read and clear) Reset Value: 0000 0000 (00h CS2 CS1 CIE2 Bit 7:6 = Reserved, always read as 0. Bit 5:4 = ...
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ST7262xxx PWM AUTO-RELOAD TIMER (Cont’d) Table 16. PWM Auto-Reload Timer Register Map and Reset Values Address Register (Hex.) Label PWMDCR1 0014h Reset Value PWMDCR0 0015h Reset Value PWMCR 0016h Reset Value ARTCSR EXCL 0017h Reset Value ARTCAR 0018h Reset Value ...
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TIMEBASE UNIT (TBU) 10.3.1 Introduction The Timebase unit (TBU) can be used to generate periodic interrupts. 10.3.2 Main Features 8-bit upcounter ■ Programmable prescaler ■ Period between interrupts: max. 8.1ms (at 8 ■ MHz f ) CPU Maskable interrupt ...
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ST7262xxx TIMEBASE UNIT (Cont’d) 10.3.5 Low Power Modes Mode Description WAIT No effect on TBU HALT TBU halted. 10.3.6 Interrupts Enable Interrupt Event Control Event Flag Bit Counter Over- OVF ITE flow Event Note: The OVF interrupt event is connected ...
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TIMEBASE UNIT (Cont’d) Table 17. TBU Register Map and Reset Values Address Register 7 Label (Hex.) TBUCV CV7 0036h Reset Value 0 TBUSR - 0037h Reset Value CV6 CV5 CV4 CAS OVF ITE ...
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ST7262xxx 10.4 SERIAL PERIPHERAL INTERFACE (SPI) 10.4.1 Introduction The Serial Peripheral Interface (SPI) allows full- duplex, synchronous, serial communication with external devices. An SPI system may consist of a master and one or more slaves however the SPI interface can ...
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SERIAL PERIPHERAL INTERFACE (Cont’d) 10.4.3.1 Functional Description A basic example of interconnections between a single master and a single slave is illustrated in Figure 40. The MOSI pins are connected together and the MISO pins are connected together. In this ...
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ST7262xxx SERIAL PERIPHERAL INTERFACE (Cont’d) 10.4.3.2 Slave Select Management As an alternative to using the SS pin to control the Slave Select signal, the application can choose to manage the Slave Select signal by software. This is configured by the ...
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SERIAL PERIPHERAL INTERFACE (Cont’d) 10.4.3.3 Master Mode Operation In master mode, the serial clock is output on the SCK pin. The clock frequency, polarity and phase are configured by software (refer to the description of the SPICSR register). Note: The ...
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ST7262xxx SERIAL PERIPHERAL INTERFACE (Cont’d) 10.4.4 Clock Phase and Clock Polarity Four possible timing relationships may be chosen by software, using the CPOL and CPHA bits (See Figure 43). Note: The idle state of SCK must correspond to the polarity ...
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SERIAL PERIPHERAL INTERFACE (Cont’d) 10.4.5 Error Flags 10.4.5.1 Master Mode Fault (MODF) Master mode fault occurs when the master device has its SS pin pulled low. When a Master mode fault occurs: – The MODF bit is set and an ...
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ST7262xxx SERIAL PERIPHERAL INTERFACE (Cont’d) 10.4.5.4 Single Master System A typical single master system may be configured, using an MCU as the master and four MCUs as slaves (see Figure 45). The master device selects the individual slave de- vices ...
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SERIAL PERIPHERAL INTERFACE (Cont’d) 10.4.6 Low Power Modes Mode Description No effect on SPI. WAIT SPI interrupt events cause the device to exit from WAIT mode. SPI registers are frozen. In HALT mode, the SPI is inactive. SPI oper- ation ...
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ST7262xxx SERIAL PERIPHERAL INTERFACE (Cont’d) 10.4.8 Register Description CONTROL REGISTER (SPICR) Read/Write Reset Value: 0000 xxxx (0xh) 7 SPIE SPE SPR2 MSTR CPOL Bit 7 = SPIE Serial Peripheral Interrupt Enable. This bit is set and cleared by software. 0: ...
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SERIAL PERIPHERAL INTERFACE (Cont’d) CONTROL/STATUS REGISTER (SPICSR) Read/Write (some bits Read Only) Reset Value: 0000 0000 (00h) 7 SPIF WCOL OVR MODF Bit 7 = SPIF Serial Peripheral Data Transfer Flag (Read only). This bit is set by hardware when ...
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ST7262xxx Table 19. SPI Register Map and Reset Values Address Register 7 Label (Hex.) SPIDR MSB 0011h Reset Value SPICR SPIE 0012h Reset Value SPICSR SPIF 0013h Reset Value 66/139 SPE SPR2 MSTR 0 0 ...
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SERIAL COMMUNICATIONS INTERFACE (SCI) 10.5.1 Introduction The Serial Communications Interface (SCI) offers a flexible means of full-duplex data exchange with external equipment requiring an industry standard NRZ asynchronous serial data format. The SCI of- fers a very wide range ...
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ST7262xxx SERIAL COMMUNICATIONS INTERFACE (Cont’d) Figure 46. SCI Block Diagram Write Transmit Data Register (TDR) TDO Transmit Shift Register RDI TRANSMIT CONTROL CR2 TIE TCIE RIE SCI INTERRUPT CONTROL TRANSMITTER CLOCK f CPU 68/139 Read Received Data Register (RDR) R8 ...
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SERIAL COMMUNICATIONS INTERFACE (Cont’d) 10.5.4 Functional Description The block diagram of the Serial Control Interface, is shown in Figure 46 It contains six dedicated reg- isters: – Two control registers (SCICR1 & SCICR2) – A status register (SCISR) – A ...
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ST7262xxx SERIAL COMMUNICATIONS INTERFACE (Cont’d) 10.5.4.2 Transmitter The transmitter can send data words of either bits depending on the M bit status. When the M bit is set, word length is 9 bits and the 9th bit ...
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SERIAL COMMUNICATIONS INTERFACE (Cont’d) 10.5.4.3 Receiver The SCI can receive data words of either bits. When the M bit is set, word length is 9 bits and the MSB is stored in the R8 bit in the ...
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ST7262xxx SERIAL COMMUNICATIONS INTERFACE (Cont’d) Figure 48. SCI Baud Rate and Extended Prescaler Block Diagram EXTENDED PRESCALER TRANSMITTER RATE CONTROL EXTENDED TRANSMITTER PRESCALER REGISTER EXTENDED RECEIVER PRESCALER REGISTER EXTENDED PRESCALER RECEIVER RATE CONTROL f CPU /PR /16 SCP1 CONVENTIONAL BAUD ...
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SERIAL COMMUNICATIONS INTERFACE (Cont’d) Framing Error A framing error is detected when: – The stop bit is not recognized on reception at the expected time, following either a de-synchroni- zation or excessive noise. – A break is received. When the ...
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ST7262xxx SERIAL COMMUNICATIONS INTERFACE (Cont’d) 10.5.4.7 Parity Control Parity control (generation of parity bit in transmis- sion and parity checking in reception) can be ena- bled by setting the PCE bit in the SCICR1 register. Depending on the frame length ...
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SERIAL COMMUNICATIONS INTERFACE (Cont’d) 10.5.4.9 Clock Deviation Causes The causes which contribute to the total deviation are: – Deviation due to transmitter error (Local TRA oscillator error of the transmitter or the trans- mitter is transmitting at a ...
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ST7262xxx SERIAL COMMUNICATIONS INTERFACE (Cont’d) 10.5.5 Low Power Modes Mode Description No effect on SCI. WAIT SCI interrupts cause the device to exit from Wait mode. SCI registers are frozen. HALT In Halt mode, the SCI stops transmitting/re- ceiving until ...
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SERIAL COMMUNICATIONS INTERFACE (Cont’d) 10.5.7 Register Description STATUS REGISTER (SCISR) Read Only Reset Value: 1100 0000 (C0h) 7 TDRE TC RDRF IDLE OR Bit 7 = TDRE Transmit data register empty. This bit is set by hardware when the content ...
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ST7262xxx SERIAL COMMUNICATIONS INTERFACE (Cont’d) CONTROL REGISTER 1 (SCICR1) Read/Write Reset Value: x000 0000 (x0h SCID M WAKE Bit Receive data bit 8. This bit is used to store the 9th bit of the ...
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SERIAL COMMUNICATIONS INTERFACE (Cont’d) CONTROL REGISTER 2 (SCICR2) Read/Write Reset Value: 0000 0000 (00h) 7 TIE TCIE RIE ILIE TE Bit 7 = TIE Transmitter interrupt enable. This bit is set and cleared by software. 0: Interrupt is inhibited 1: ...
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ST7262xxx SERIAL COMMUNICATIONS INTERFACE (Cont’d) DATA REGISTER (SCIDR) Read/Write Reset Value: Undefined Contains the Received or Transmitted data char- acter, depending on whether it is read from or writ- ten to. 7 DR7 DR6 DR5 DR4 DR3 The Data register ...
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SERIAL COMMUNICATIONS INTERFACE (Cont’d) EXTENDED RECEIVE PRESCALER DIVISION REGISTER (SCIERPR) Read/Write Reset Value: 0000 0000 (00h) Allows setting of the Extended Prescaler rate divi- sion factor for the receive circuit. 7 ERPR ERPR ERPR ERPR ERPR ...
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ST7262xxx SERIAL COMMUNICATIONS INTERFACE (Cont’d) Table 22. SCI Register Map and Reset Values Address Register Name (Hex.) SCIERPR ERPR7 1D Reset Value SCIETPR ETPR7 1E Reset Value SCISR 20 Reset Value SCIDR 21 Reset Value SCIBRR 22 Reset Value SCICR1 ...
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USB INTERFACE (USB) 10.6.1 Introduction The USB Interface implements a low-speed func- tion interface between the USB and the ST7 mi- crocontroller highly integrated circuit which includes the transceiver, 3.3 voltage regulator, SIE and DMA. No ...
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ST7262xxx USB INTERFACE (Cont’d) 10.6.4 Register Description DMA ADDRESS REGISTER (DMAR) Read / Write Reset Value: Undefined 7 DA15 DA14 DA13 DA12 DA11 Bits 7:0=DA[15:8] DMA address bits 15-8. Software must write the start address of the DMA memory area ...
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USB INTERFACE (Cont’d) PID REGISTER (PIDR) Read only Reset Value: xx00 0000 (x0h) 7 TP3 TP2 Bits 7:6 = TP[3:2] Token PID bits 3 & 2. USB token PIDs are encoded in four bits. TP[3:2] correspond to ...
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ST7262xxx USB INTERFACE (Cont’d) Bit 3 = IOVR Interrupt overrun. This bit is set when hardware tries to set ERR, or SOF before they have been cleared by software overrun detected 1: Overrun detected Bit 2 = ESUSP ...
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USB INTERFACE (Cont’d) DEVICE ADDRESS REGISTER (DADDR) Read / Write Reset Value: 0000 0000 (00h ADD6 ADD5 ADD4 ADD3 Bit 7 = Reserved. Forced by hardware to 0. Bits 6:0 = ADD[6:0] Device address, 7 bits. Software must ...
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ST7262xxx USB INTERFACE (Cont’d) ENDPOINT n REGISTER B (EPnRB) Read / Write Reset Value: 0000 xxxx (0xh) 7 DTOG STAT STAT CTRL _RX _RX1 _RX0 These registers (EP1RB and EP2RB) are used for controlling data reception on Endpoints 1 and ...
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USB INTERFACE (Cont’d) 10.6.5 Programming Considerations The interaction between the USB interface and the application program is described below. Apart from system reset, action is always initiated by the USB interface, driven by one of the USB events associated with ...
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USB INTERFACE (Cont’d) Table 23. USB Register Map and Reset Values Address Register 7 Name (Hex.) PIDR TP3 25 Reset Value x DMAR DA15 26 Reset Value x IDR DA7 27 Reset Value x ISTR SUSP 28 Reset Value 0 ...
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A/D CONVERTER (ADC) 10.7.1 Introduction The on-chip Analog to Digital Converter (ADC) pe- ripheral is a 10-bit, successive approximation con- verter with internal sample and hold circuitry. This peripheral has multiplexed analog input channels (refer ...
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A/D CONVERTER (ADC) (Cont’d) 10.7.3.4 A/D Conversion Conversion can be performed in One-Shot or Con- tinuous mode. Continuous mode is typically used for monitoring a single channel. One-shot mode should be used when the application requires in- puts from ...
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A/D CONVERTER (ADC) (Cont’d) To read only 8 bits, perform the following steps: 1. Wait for interrupt or poll the EOC bit 2. Read ADCDRMSB The EOC bit is reset by hardware once the AD- CDRMSB is read. To ...
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A/D CONVERTER (ADC) (Cont’d) 10.7.6 Register Description CONTROL/STATUS REGISTER (ADCCSR) Read/Write (Except bit 7 read only) Reset Value: 0000 0000 (00h) 7 ONE EOC SPEED ADON ITE SHOT Bit 7 = EOC End of Conversion This bit is set ...
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INSTRUCTION SET 11.1 CPU ADDRESSING MODES The CPU features 17 different addressing modes which can be classified in seven main groups: Addressing Mode Example Inherent nop Immediate ld A,#$55 Direct ld A,$55 Indexed ld A,($55,X) Indirect ld A,([$55],X) Relative ...
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INSTRUCTION SET OVERVIEW (Cont’d) 11.1.1 Inherent All Inherent instructions consist of a single byte. The opcode fully specifies all the required informa- tion for the CPU to process the operation. Inherent Instruction NOP No operation TRAP S/W Interrupt Wait For ...
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INSTRUCTION SET OVERVIEW (Cont’d) 11.1.6 Indirect Indexed (Short, Long) This is a combination of indirect and short indexed addressing modes. The operand is referenced by its memory address, which is defined by the un- signed addition of an index register ...
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INSTRUCTION SET OVERVIEW (Cont’d) 11.2 INSTRUCTION GROUPS The ST7 family devices use an Instruction Set consisting of 63 instructions. The instructions may Load and Transfer Stack operation Increment/Decrement Compare and Tests Logical operations Bit Operation Conditional Bit Test and Branch ...
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INSTRUCTION SET OVERVIEW (Cont’d) Mnemo Description ADC Add with Carry ADD Addition AND Logical And BCP Bit compare A, Memory BRES Bit Reset BSET Bit Set BTJF Jump if bit is false (0) BTJT Jump if bit is true (1) ...
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INSTRUCTION SET OVERVIEW (Cont’d) Mnemo Description JRULE Jump Load MUL Multiply NEG Negate (2's compl) NOP No Operation OR OR operation POP Pop from the Stack PUSH Push onto the Stack RCF Reset ...
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ELECTRICAL CHARACTERISTICS 12.1 PARAMETER CONDITIONS Unless otherwise specified, all voltages are re- ferred 12.1.1 Minimum and Maximum Values Unless otherwise specified the minimum and max- imum values are guaranteed in the worst condi- tions of ...
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ABSOLUTE MAXIMUM RATINGS Stresses above those listed as “absolute maxi- mum ratings” may cause permanent damage to the device. This is a stress rating only and func- tional operation of the device under these condi- 12.2.1 Voltage Characteristics Symbol ...
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Thermal Characteristics Symbol T Storage temperature range STG T Maximum junction temperature J Notes: 1. The maximum chip-junction temperature is based on technology characteristics. 12.3 OPERATING CONDITIONS 12.3.1 General Operating Conditions (standard voltage ROM and Flash devices) Symbol Parameter ...
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SUPPLY CURRENT CHARACTERISTICS The following current consumption specified for the ST7 functional operating modes over tempera- ture range does not take into account the clock source current consumption. To get the total de- vice consumption, the two current values ...
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Subject to general operating conditions for V 12.5.1 General Timings Symbol Parameter t Instruction cycle time c(INST) Interrupt reaction time t = Δt v(IT v(IT) c(INST) 1. Data based on typical ...
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CLOCK AND TIMING CHARACTERISTICS (Cont’d) 12.5.3 External Clock Source Symbol Parameter V OSCIN input pin high level voltage OSCINH V OSCIN input pin low level voltage OSCINL t w(OSCINH) OSCIN high or low time t w(OSCINL) t r(OSCIN) OSCIN rise ...
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MEMORY CHARACTERISTICS Subject to general operating conditions for f 12.6.1 RAM and Hardware Registers Symbol Parameter V Data retention mode RM Note 1: Guaranteed by design. Not tested in production. 12.6.2 FLASH Memory Operating Conditions MHz. ...
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EMC CHARACTERISTICS Susceptibility tests are performed on a sample ba- sis during product characterization. 12.7.1 Functional EMS Susceptibility) Based on a simple running application on the product (toggling 2 LEDs through I/O ports), the product is stressed by two ...
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... Static latchup class Notes: 1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the JEDEC spec- ifications, that means when a device belongs to Class A it exceeds the JEDEC standard. B Class strictly covers all the JEDEC criteria (international standard). ...
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I/O PORT PIN CHARACTERISTICS 12.8.1 General Characteristics Subject to general operating conditions for V Symbol Parameter V Input low level voltage IL V Input high level voltage IH V Input voltage IN V Schmitt trigger voltage hysteresis hys I ...
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I/O PORT PIN CHARACTERISTICS (Cont’d) 12.8.2 Output Driving Current Subject to general operating condition for V Symbol Parameter Output low level voltage for a standard I/O pin when pins are sunk at same time (see Figure 64) ...
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I/O PORT PIN CHARACTERISTICS (Cont’d) Figure 68. Typical V vs 0.25 0.2 0.15 0.1 0.05 0 3.5 4 4.5 V Figure 69. Typical V vs 0.3 0.25 0.2 0.15 0.1 0.05 0 3.5 4 4.5 V ...
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I/O PORT PIN CHARACTERISTICS (Cont’d) Figure 71. Typical 0.09 0.08 0.07 0.06 0.05 0.04 0.03 0.02 0.01 0 3.5 4 4.5 Vdd (V) 12.9 CONTROL PIN CHARACTERISTICS 12.9.1 Asynchronous RESET Pin Subject to general operating conditions ...
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CONTROL PIN CHARACTERISTICS (Cont’d) Figure 72. Typical I vs 0.0 -20.0 -40.0 -60.0 -80.0 -100.0 -120.0 3.0 3.5 4.0 4.5 5.0 Vdd (V) Figure 74. Typical V vs 0.3 0.25 0.2 0.15 0.1 0. ...
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CONTROL PIN CHARACTERISTICS (Cont’d) Figure 75. RESET pin protection when LVD is enabled. Required EXTERNAL RESET 0.01μF Figure 76. RESET pin protection when LVD is disabled. USER EXTERNAL RESET CIRCUIT 0.01μF Required Note 1: – The reset network protects the ...
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TIMER PERIPHERAL CHARACTERISTICS Subject to general operating conditions for and T unless otherwise specified. CPU A 12.10.1 8-Bit PWM-ART Auto-Reload Timer Symbol Parameter t PWM resolution time res(PWM) f ART external clock frequency EXT f PWM ...
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COMMUNICATION INTERFACE CHARACTERISTICS 12.11.1 USB - Universal Bus Interface (Operating conditions +70° USB DC Electrical Characteristics Parameter Differential Input Sensitivity Differential Common Mode Range Single Ended Receiver Threshold Static Output Low Static Output ...
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COMMUNICATION INTERFACE CHARACTERISTICS (Cont’d) 12.11.2 SPI - Serial Peripheral Interface Subject to general operating condition for and T unless otherwise specified. CPU A Symbol Parameter f SCK SPI clock frequency 1/t c(SCK) t r(SCK) SPI clock rise ...
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COMMUNICATION INTERFACE CHARACTERISTICS (Cont’d) Figure 79. SPI Slave Timing Diagram with CPHA=1 SS INPUT t su(SS) CPHA=1 CPOL=0 CPHA=1 CPOL=1 t w(SCKH) t a(SO) t w(SCKL) see MISO OUTPUT HZ note 2 t MOSI INPUT Figure 80. SPI Master Timing ...
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ADC CHARACTERISTICS Subject to general operating conditions for V Symbol Parameter f ADC clock frequency ADC V Conversion voltage range AIN R External input impedance AIN C External capacitor on analog input AIN f Variation frequency of analog ...
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ADC CHARACTERISTICS (Cont’d) 12.12.0.1 Analog Power Supply and Reference Pins Depending on the MCU pin count, the package may feature separate V and V DDA er supply pins. These pins supply power to the A/D converter cell and function as ...
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ADC CHARACTERISTICS (Cont’d) 12.12.1 ADC Accuracy Table 27 MHz, f CPU ADC Symbol Parameter |E | Total unadjusted error Offset error Gain Error Differential linearity error ...
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Figure 85. ADC Accuracy Characteristics Digital Result ADCDR 1023 – 1022 V V DDA 1LSB = ---------------------------------------- - IDEAL 1021 1024 LSB SSA ...
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PACKAGE CHARACTERISTICS In order to meet environmental requirements, ST offers this device in different grades of ECO- PACK® packages, depending on their level of en- vironmental compliance. ECOPACK 13.1 PACKAGE MECHANICAL DATA Figure 86. 44-Pin Low Profile Quad Flat ...
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Figure 87. 42-Pin Plastic Dual In-Line Package, Shrink 600-mil Width b2 D Figure 88. 34-Pin Plastic Small Outline Package, Shrink 300-mil Width 0.015 GAGE PLANE eC ...
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Figure 89. 32-Pin Plastic Dual In-Line Package, Shrink 400-mil Width Figure 90. 20-Pin Plastic Small Outline Package, 300-mil Width 126/139 45× L ...
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Figure 91. 20-Pin Plastic Dual In-Line Package, 300-mil Width Doc ID 6996 Rev 5 mm Dim. Min Typ Max Min A 5. 0.38 ...
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... OP- TION LIST appended. Refer to application note AN1635 for information on the counter listing returned by ST after code has been transferred. The STMicroelectronics Sales Organization will be pleased to provide detailed information on con- tractual points. Doc ID 6996 Rev 5 section 4.3.1 on page 14 ...
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... DEVICE CONFIGURATION AND ORDERING INFORMATION (Cont’d) Table 28. Supported part numbers Part Number ST72F623F2B1 ST72F623F2M1 ST72F622L2M1 ST72F621K4B1 ST72F621L4M1 ST72F621J4B1 ST72F621J4T1 ST72623F2B1 ST72623F2M1 ST72622L2M1 ST72621K4B1 ST72621L4M1 ST72621J4B1 ST72621J4T1 Contact ST sales office for product availability Program Memory (Bytes) 8K FLASH 16K FLASH 16K FLASH ...
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... DEVELOPMENT TOOLS STMicroelectronics offers a range of hardware and software development tools for the ST7 micro- controller family. Full details of tools available for the ST7 from third party manufacturers can be ob- tain from the STMicroelectronics Internet site: ➟ http//mcu.st.com. Tools from these manufacturers include C compli- ers, emulators and gang programmers ...
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... Reference/ROM Code *The ROM code name is assigned by STMicroelectronics. ROM code must be sent in .S19 format. .Hex extension cannot be processed. Device Type/Memory Size/Package (check only one option): ...
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ST7 APPLICATION NOTES Table 31. ST7 Application Notes IDENTIFICATION DESCRIPTION APPLICATION EXAMPLES AN1658 SERIAL NUMBERING IMPLEMENTATION AN1720 MANAGING THE READ-OUT PROTECTION IN FLASH MICROCONTROLLERS AN1755 A HIGH RESOLUTION/PRECISION THERMOMETER USING ST7 AND NE555 AN1756 CHOOSING A DALI IMPLEMENTATION STRATEGY ...
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Table 31. ST7 Application Notes IDENTIFICATION DESCRIPTION AN1947 ST7MC PMAC SINE WAVE MOTOR CONTROL SOFTWARE LIBRARY GENERAL PURPOSE AN1476 LOW COST POWER SUPPLY FOR HOME APPLIANCES AN1526 ST7FLITE0 QUICK REFERENCE NOTE AN1709 EMC DESIGN FOR ST MICROCONTROLLERS AN1752 ST72324 QUICK ...
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Table 31. ST7 Application Notes IDENTIFICATION DESCRIPTION AN1039 ST7 MATH UTILITY ROUTINES AN1064 WRITING OPTIMIZED HIWARE C LANGUAGE FOR ST7 AN1071 HALF DUPLEX USB-TO-SERIAL BRIDGE USING THE ST72611 USB MICROCONTROLLER AN1106 TRANSLATING ASSEMBLY CODE FROM HC05 TO ST7 PROGRAMMING ST7 ...
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IMPORTANT NOTES Refer to Table 32 which provides a list of the trace codes for each of the recent silicon revisions. Silicon revisions are identifiable: – on the device package, by the last letter of the Trace Code marked ...
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SCI WRONG BREAK DURATION Description A single break character is sent by setting and re- setting the SBK bit in the SCICR2 register. In some cases, the break character may have a long- er duration than expected: – 20 ...
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Figure 92. Revision Marking on Box Label and Device Marking Note: Refer also to Table 32 on page 135 TYPE xxxx Internalxxx$xx Trace Code LAST LETTER OF TRACE CODE ON DEVICE INDICATES SILICON REV. for additional revision identification notes Doc ...
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REVISION HISTORY Description of the changes between the current release of the specification and the previous one. Date Revision Clarification of Flash read-out protection in Removed “optional” for V Added one note in Added caution to Changed Changed Changed ...
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... Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...