ST72F621L4M1 STMicroelectronics, ST72F621L4M1 Datasheet - Page 42

• Manufacturer Part Number: ST72F621L4M1
• Description: IC MCU 8BIT LS 16K 34-SOIC
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST72F621L4M1

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 34-SOIC (7.5mm Width)
• Processor Series: ST72F6x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: SCI, SPI, USB
• Maximum Clock Frequency: 12 MHz
• Number Of Programmable I/os: 23
• Number Of Timers: 2
• Operating Supply Voltage: 4 V to 5.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit
• For Use With: 497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: In Transition
• Other names: 497-2112-5

ST7262xxx
WATCHDOG TIMER (Cont’d)
10.1.4 Software Watchdog Option
If Software Watchdog is selected by option byte,
the watchdog is disabled following a reset. Once
activated it cannot be disabled, except by a reset.
The T6 bit can be used to generate a software re-
set (the WDGA bit is set and the T6 bit is cleared).
10.1.5 Hardware Watchdog Option
If Hardware Watchdog is selected by option byte,
the watchdog is always active and the WDGA bit in
the CR is not used.
10.1.6 Low Power Modes
WAIT Instruction
No effect on Watchdog.
HALT Instruction
Halt mode can be used when the watchdog is en-
abled. When the oscillator is stopped, the WDG
stops counting and is no longer able to generate a
reset until the microcontroller receives an external
interrupt or a reset.
If an external interrupt is received, the WDG re-
starts counting after 514 CPU clocks. In the case
of the Software Watchdog option, if a reset is gen-
erated, the WDG is disabled (reset state).
Recommendations
– Make sure that an external event is available to
– Before executing the HALT instruction, refresh
– When using an external interrupt to wake up the
Table 15. Watchdog Timer Register Map and Reset Values
42/139
wake up the microcontroller from Halt mode.
the WDG counter, to avoid an unexpected WDG
reset immediately after waking up the microcon-
troller.
microcontroller, reinitialize the corresponding I/O
as Input before executing the HALT instruction.
The main reason for this is that the I/O may be
wrongly configured due to external interference
or by an unforeseen logical condition.
Address
(Hex.)
0Dh
WDGCR
Reset Value
Register
Label
WDGA
7
0
T6
6
1
T5
5
1
Doc ID 6996 Rev 5
– The opcode for the HALT instruction is 0x8E. To
– As the HALT instruction clears the I bit in the CC
10.1.7 Interrupts
None.
10.1.8 Register Desc4ription
CONTROL REGISTER (CR)
Read/Write
Reset Value: 0111 1111 (7Fh)
Bit 7 = WDGA Activation bit.
This bit is set by software and only cleared by
hardware after a reset. When WDGA = 1, the
watchdog can generate a reset.
0: Watchdog disabled
1: Watchdog enabled
Note: This bit is not used if the hardware watch-
dog option is enabled by option byte.
Bits 6:0 = T[6:0] 7-bit timer (MSB to LSB).
These bits contain the decremented value. A reset
is produced when it rolls over from 40h to 3Fh (T6
becomes cleared).
WDGA
avoid an unexpected HALT instruction due to a
program counter failure, it is advised to clear all
occurrences of the data value 0x8E from memo-
ry. For example, avoid defining a constant in
ROM with the value 0x8E.
register to allow interrupts, the user may choose
to clear all pending interrupt bits before execut-
ing the HALT instruction. This avoids entering
other peripheral interrupt routines after executing
the external interrupt routine corresponding to
the wake-up event (reset or external interrupt).
7
T4
4
1
T6
T3
3
1
T5
T4
T2
2
1
T3
T2
T1
1
1
T1
T0
0
1
T0
0