HD6413003TF16V Renesas Electronics America, HD6413003TF16V Datasheet - Page 178

MCU 5V 0K PB-FREE 112-QFP

HD6413003TF16V

Manufacturer Part Number
HD6413003TF16V
Description
MCU 5V 0K PB-FREE 112-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Datasheet

Specifications of HD6413003TF16V

Core Size
16-Bit
Oscillator Type
Internal
Core Processor
H8/300H
Speed
16MHz
Connectivity
SCI
Peripherals
DMA, PWM, WDT
Number Of I /o
50
Program Memory Type
ROMless
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Operating Temperature
-20°C ~ 75°C
Package / Case
112-QFP
No. Of I/o's
58
Ram Memory Size
512Byte
Cpu Speed
16MHz
No. Of Timers
11
No. Of Pwm Channels
4
Digital Ic Case Style
QFP
Supply Voltage
RoHS Compliant
Controller Family/series
H8/300H
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6413003TF16V
Manufacturer:
ITT
Quantity:
12 000
Part Number:
HD6413003TF16V
Manufacturer:
RENESAS
Quantity:
36
Part Number:
HD6413003TF16V
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
Example 4: Connection to Two 4-Mbit DRAM Chips (16-Mbyte Mode): Figure 7-13 shows
an example of interconnections to two 2CAS 4-Mbit DRAM chips, and the corresponding address
map. Up to four DRAM chips can be connected to area 3 by decoding upper address bits A
and A
Figure 7-14 shows a setup procedure to be followed by a program for this example. The DRAM
in this example has 9-bit row addresses and 9-bit column addresses. Both chips must be refreshed
simultaneously, so the RFSH pin must be used.
Figure 7-13 Interconnections and Address Map for Multiple 2CAS 4-Mbit DRAM Chips
20
.
H8/3003
H'600000
H'67FFFF
H'680000
H'6FFFFF
H'700000
H'7FFFFF
D
A to A
15
9
RFSH
HWR
to D
LWR
CS
A
RD
19
1
3
0
DRAM area
DRAM area
Not used
No. 1
No. 2
a. Interconnections (example)
b. Address map
(Example)
158
Area 3 (16-Mbyte mode)
2
row address, 9-bit column
address, and
CAS
A to A
RAS
UCAS
LCAS
WE
OE
I/O
A to A
RAS
UCAS
LCAS
WE
OE
I/O
8
8
15
15
4-Mbit DRAM with 9-bit
to I/O
to I/O
0
0
0
0
16-bit organization
No. 1
No. 2
19

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