HD6413003TF16V Renesas Electronics America, HD6413003TF16V Datasheet - Page 344

• Manufacturer Part Number: HD6413003TF16V
• Description: MCU 5V 0K PB-FREE 112-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD6413003TF16V

• Core Size: 16-Bit
• Oscillator Type: Internal
• Core Processor: H8/300H
• Speed: 16MHz
• Connectivity: SCI
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 50
• Program Memory Type: ROMless
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• No. Of I/o's: 58
• Ram Memory Size: 512Byte
• Cpu Speed: 16MHz
• No. Of Timers: 11
• No. Of Pwm Channels: 4
• Digital Ic Case Style: QFP
• Supply Voltage: RoHS Compliant
• Controller Family/series: H8/300H
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

•
H'FFFF
H'0000
STR0 to
STR4 bit
OVF
Free-running and periodic counter operation
A reset leaves the counters (TCNTs) in ITU channels 0 to 4 all set as free-running counters. A
free-running counter starts counting up when the corresponding bit in TSTR is set to 1. When
the count overflows from H'FFFF to H'0000, the overflow flag (OVF) is set to 1 in the timer
status register (TSR). If the corresponding OVIE bit is set to 1 in the timer interrupt enable
register, a CPU interrupt is requested. After the overflow, the counter continues counting up
from H'0000. Figure 10-15 illustrates free-running counting.
When a channel is set to have its counter cleared by compare match, in that channel TCNT
operates as a periodic counter. Select the output compare function of GRA or GRB, set bit
CCLR1 or CCLR0 in the timer control register (TCR) to have the counter cleared by compare
match, and set the count period in GRA or GRB. After these settings, the counter starts
counting up as a periodic counter when the corresponding bit is set to 1 in TSTR. When the
count matches GRA or GRB, the IMFA or IMFB flag is set to 1 in TSR and the counter is
cleared to H'0000. If the corresponding IMIEA or IMIEB bit is set to 1 in TIER, a CPU
interrupt is requested at this time. After the compare match, TCNT continues counting up
from H'0000. Figure 10-16 illustrates periodic counting.
TCNT value
Figure 10-15 Free-Running Counter Operation
324
Time