HD6413003TF16V Renesas Electronics America, HD6413003TF16V Datasheet - Page 85

• Manufacturer Part Number: HD6413003TF16V
• Description: MCU 5V 0K PB-FREE 112-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD6413003TF16V

• Core Size: 16-Bit
• Oscillator Type: Internal
• Core Processor: H8/300H
• Speed: 16MHz
• Connectivity: SCI
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 50
• Program Memory Type: ROMless
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• No. Of I/o's: 58
• Ram Memory Size: 512Byte
• Cpu Speed: 16MHz
• No. Of Timers: 11
• No. Of Pwm Channels: 4
• Digital Ic Case Style: QFP
• Supply Voltage: RoHS Compliant
• Controller Family/series: H8/300H
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4.1 Overview
4.1.1 Exception Handling Types and Priority
As table 4-1 indicates, exception handling may be caused by a reset, trap instruction, or interrupt.
Exception handling is prioritized as shown in table 4-1. If two or more exceptions occur
simultaneously, they are accepted and processed in priority order. Trap instruction exceptions are
accepted at all times in the program execution state.
Table 4-1 Exception Types and Priority
Priority Exception Type
High
Low
4.1.2 Exception Handling Operation
Exceptions originate from various sources. Trap instructions and interrupts are handled as follows.
1.
2.
3.
For a reset exception, steps 2 and 3 above are carried out.
The program counter (PC) and condition code register (CCR) are pushed onto the stack.
The CCR interrupt mask bit is set to 1.
A vector address corresponding to the exception source is generated, and program execution
starts from that address.
Reset
Interrupt
Trap instruction (TRAPA) Started by execution of a trap instruction (TRAPA)
Section 4 Exception Handling
Start of Exception Handling
Starts immediately after a low-to-high transition at the RES pin
Interrupt requests are handled when execution of the current
instruction or handling of the current exception is completed
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