HD6473834HV Renesas Electronics America, HD6473834HV Datasheet - Page 225

• Manufacturer Part Number: HD6473834HV
• Description: MCU 5V 32K PB-FREE 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Lr

Specifications of HD6473834HV

• Core Processor: H8/300L
• Core Size: 8-Bit
• Speed: 5MHz
• Connectivity: SCI
• Peripherals: LCD, PWM
• Number Of I /o: 71
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: OTP
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Compare Match Flag Set Timing: The compare match flags (CMFH or CMFL) are set to 1
when a compare match occurs between TCF and OCRF. A compare match signal is generated in
the final state in which the values match (when TCF changes from the matching count value to the
next value). When TCF and OCRF match, a compare match signal is not generated until the next
counter clock pulse.
Timer F Operation States: Table 9.13 summarizes the timer F operation states.
Table 9.13 Timer F Operation States
Operation Mode
TCF
OCRF
TCRF
TCSRF
9.5.5
The following conflicts can arise in timer F operation.
208
16-bit timer mode
The output at pin TMOFH toggles when all 16 bits match and a compare match signal is
generated. If the compare match signal occurs at the same time as new data is written in TCRF
by a MOV instruction, however, the new value written in bit TOLH will be output at pin
TMOFH. The TMOFL output in 16-bit mode is indeterminate, so this output should not be
used. Use the pin as a general input or output port.
If an OCRFL write occurs at the same time as a compare match signal, the compare match
signal is inhibited. If a compare match occurs between the written data and the counter value,
however, a compare match signal will be generated at that point. The compare match signal is
output in synchronization with the TCFL clock, so if this clock is stopped no compare match
signal will be generated, even if a compare match occurs.
Compare match flag CMFH is set when all 16 bits match and a compare match signal is
generated; bit CMFL is set when the setting conditions are met for the lower 8 bits.
The overflow flag (OVFH) is set when TCF overflows; bit OVFL is set if the setting
conditions are met when the lower 8 bits overflow. If a write to TCFL occurs at the same time
as an overflow signal, the overflow signal is not output.
Application Notes
Reset
Reset
Reset
Reset
Reset
Active
Functions
Functions
Functions
Functions
Sleep
Functions
Retained
Retained
Retained
Watch
Halted
Retained
Retained
Retained
Sub-
active
Halted
Retained
Retained
Retained
Sub-
sleep
Halted
Retained
Retained
Retained
Standby
Halted
Retained
Retained
Retained