HD6473834HV Renesas Electronics America, HD6473834HV Datasheet - Page 316

• Manufacturer Part Number: HD6473834HV
• Description: MCU 5V 32K PB-FREE 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Lr

Specifications of HD6473834HV

• Core Processor: H8/300L
• Core Size: 8-Bit
• Speed: 5MHz
• Connectivity: SCI
• Peripherals: LCD, PWM
• Number Of I /o: 71
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: OTP
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

11.2.2
PWDRU and PWDRL form a 14-bit write-only register, with the upper 6 bits assigned to PWDRU
and the lower 8 bits to PWDRL. The value written to PWDRU and PWDRL gives the total high-
level width of one PWM waveform cycle.
When 14-bit data is written to PWDRU and PWDRL, the register contents are latched in the PWM
waveform generator, updating the PWM waveform generation data. The 14-bit data should always
be written in the following sequence, first to PWDRL and then to PWDRU.
1. Write the lower 8 bits to PWDRL.
2. Write the upper 6 bits to PWDRU.
PWDRU and PWDRL are write-only registers. If they are read, all bits are read as 1.
Upon reset, PWDRU and PWDRL are initialized to H'C000.
11.3
When using the 14-bit PWM, set the registers in the following sequence.
1. Set bit PWM in port mode register 1 (PMR1) to 1 so that pin P1
2. Set bit PWCR0 in the PWM control register (PWCR) to select a conversion period of either
3. Set the output waveform data in PWM data registers U and L (PWDRU/L). Be sure to write in
output.
32,768/ (PWCR0 = 1) or 16,384/ (PWCR0 = 0).
the correct sequence, first PWDRL then PWDRU. When data is written to PWDRU, the data
in these registers will be latched in the PWM waveform generator, updating the PWM
waveform generation in synchronization with internal signals.
One conversion period consists of 64 pulses, as shown in figure 11.2. The total of the high-
level pulse widths during this period (T
This relation can be represented as follows.
where t is the PWM input clock period, either 2/ (bit PWCR0 = 0) or 4/ (bit PWCR0 = 1).
Example: Settings in order to obtain a conversion period of 8,192 µs:
T
PWM Data Registers U and L (PWDRU, PWDRL)
Operation
H
= (data value in PWDRU and PWDRL + 64)
When bit PWCR0 = 0, the conversion period is 16,384/ , so must be 2 MHz. In
this case t
When bit PWCR0 = 1, the conversion period is 32,768/ , so must be 4 MHz. In
this case t
fn
fn
= 128 µs, with 1/ (resolution) = 0.5 µs.
= 128 µs, with 2/ (resolution) = 0.5 µs.
H
) corresponds to the data in PWDRU and PWDRL.
t /2
4
/PWM is designated for PWM
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