HD6473834HV Renesas Electronics America, HD6473834HV Datasheet - Page 312

• Manufacturer Part Number: HD6473834HV
• Description: MCU 5V 32K PB-FREE 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Lr

Specifications of HD6473834HV

• Core Processor: H8/300L
• Core Size: 8-Bit
• Speed: 5MHz
• Connectivity: SCI
• Peripherals: LCD, PWM
• Number Of I /o: 71
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: OTP
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

To avoid the situation described above, after RDRF is confirmed to be 1, RDR should only be read
once and should not be read twice or more.
When the same data must be read more than once, the data read the first time should be copied to
RAM, for example, and the copied data should be used. An alternative is to read RDR but leave a
safe margin of time before reception of the next frame is completed. In synchronous mode, all
reads of RDR should be completed before bit 7 is received. In asynchronous mode, all reads of
RDR should be completed before the stop bit is received.
Caution on Switching of SCK
synchronous mode and is then switched to a general input/output pin (a pin with a different
function), the pin outputs a low level signal for half a system clock ( ) cycle immediately after it is
switched.
This can be prevented by either of the following methods according to the situation.
1. When an SCK
Communica-
tion line
RDRF
RDR
When stopping data transfer, issue one instruction to clear bits TE and RE to 0 and to set bits
CKE1 and CKE0 in SCR3 to 1 and 0, respectively. In this case, bit COM in SMR should be
left 1. The above prevents SCK
intermediate level of voltage from being applied to SCK
be pulled up to the V
Figure 10.28 Relationship between Data and RDR Read Timing
3
function is switched from clock output to non clock-output
CC
level via a resistor, or supplied with output from an external device.
Frame 1
Data 1
3
Function: If pin SCK
3
from being used as a general input/output pin. To avoid an
3
is used as a clock output pin by SCI3 in
RDR read
Frame 2
3
Data 2
Data 1
, the line connected to SCK
At A , data 1 is read.
At B , data 2 is read.
RDR read
A
B
Frame 3
Data 3
Data 2
3
should
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