HD6417032F20V Renesas Electronics America, HD6417032F20V Datasheet - Page 296

SH1 ROMLESS LEAD FREE

HD6417032F20V

Manufacturer Part Number
HD6417032F20V
Description
SH1 ROMLESS LEAD FREE
Manufacturer
Renesas Electronics America
Series
SuperH® SH7030r
Datasheet

Specifications of HD6417032F20V

Core Processor
SH-1
Core Size
32-Bit
Speed
20MHz
Connectivity
EBI/EMI, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
32
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
112-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417032F20V
Manufacturer:
TI
Quantity:
201
Part Number:
HD6417032F20V
Manufacturer:
RENESAS
Quantity:
20
Section 10 16-Bit Integrated Timer Pulse Unit (ITU)
10.4.4
PWM mode is controlled using both GRA and GRB in pairs. The PWM waveform is output from
the TIOCA output pin. The PWM waveform’s 1 output timing is set in GRA and the 0 output
timing is set in GRB. A PWM waveform with a duty cycle between 0% and 100% can be output
from the TIOCA pin by selecting either compare match GRA or GRB as the counter clear source
for the timer counter. All five channels can be set to PWM mode.
Table 10.11 lists the combinations of PWM output pins and registers. Note that when GRA and
GRB are set to the same value, the output will not change even if a compare match occurs.
Table 10.11 Combinations of PWM Output Pins and Registers
Channel
0
1
2
3
4
Procedure for Selecting PWM Mode (Figure 10.28):
1. Set bits TPSC2–TPSC0 in TCR to select the counter clock source. If an external clock source
2. Set CCLR1 and CCLR0 in TCR to select the counter clear source.
3. Set the time at which the PWM waveform should go to 1 in GRA.
4. Set the time at which the PWM waveform should go to 0 in GRB.
5. Set the PWM bit in TMDR to select PWM mode. When PWM mode is selected, regardless of
6. Set the STR bit in TSTR to start the TCNT count.
Rev. 7.00 Jan 31, 2006 page 268 of 658
REJ09B0272-0700
is selected, set bits CKEG1 and CKEG0 in TCR to select the desired edge of the external clock
signal.
the contents of TIOR, GRA and GRB become output compare registers specifying the times at
which the PWM waveform goes high and low. TIOCA becomes a PWM output pin. TIOCB
functions according to the setting of bits IOB1 and IOB0 in TIOR.
PWM Mode
Output Pin
TIOCA0
TIOCA1
TIOCA2
TIOCA3
TIOCA4
1 Output
GRA0
GRA1
GRA2
GRA3
GRA4
0 Output
GRB0
GRB1
GRB2
GRB3
GRB4

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