HD6417032F20V Renesas Electronics America, HD6417032F20V Datasheet - Page 625

SH1 ROMLESS LEAD FREE

HD6417032F20V

Manufacturer Part Number
HD6417032F20V
Description
SH1 ROMLESS LEAD FREE
Manufacturer
Renesas Electronics America
Series
SuperH® SH7030r
Datasheet

Specifications of HD6417032F20V

Core Processor
SH-1
Core Size
32-Bit
Speed
20MHz
Connectivity
EBI/EMI, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
32
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
112-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417032F20V
Manufacturer:
TI
Quantity:
201
Part Number:
HD6417032F20V
Manufacturer:
RENESAS
Quantity:
20
Bit
11–8
7
6
5
4
3
2
1
0
Notes: 1. Only valid in channels 0 and 1.
Bit name
Resource select bits
3–0 (RS3–RS0) (cont)
Acknowledge mode
bit (AM) *
Acknowledge level
bit (AL) *
DREQ select bit
(DS) *
Transfer bus mode bit 0
(TM)
Transfer size bit (TS)
Interrupt enable bit
(IE)
Transfer end flag bit
(TE)
DMA enable bit (DE)
2. Transfer to external device from memory mapped external device or external memory
3. Transfer from external device to memory mapped external device or external memory
4. Dual address mode.
with DACK.
with DACK.
1
1
1
Value
1 0 1 1 IMIA3 (input capture A/compare match A interrupt
1 1 0 0 Auto request (transfer request automatically generated
1 1 0 1 ADI (A/D conversion end interrupt request of on-chip
1 1 1 0 Reserved (cannot be set)
1 1 1 1 Reserved (cannot be set)
0
1
0
1
0
1
1
0
1
0
1
0
1
0
1
DACK output in read cycle
DACK is active-high signal
Cycle-steal mode
DMA transfer disabled
Description
request of on-chip ITU3) *
within DMAC) *
A/D converter)
DACK output in write cycle
DACK is active-low signal
DREQ detected at low
DREQ detected on falling edge
Burst mode
Byte (8 bits)
Word (16 bits)
Interrupt request disabled
Interrupt request enabled
DMA transferring or DMA transfer halted (Initial value)
Clear Conditions: TE bit read and then 0 written in TE
DMA transfer ends normally
DMA transfer enabled
Appendix A On-Chip Supporting Module Registers
Rev. 7.00 Jan 31, 2006 page 597 of 658
4
4
REJ09B0272-0700
(Initial value)
(Initial value)
(Initial value)
(Initial value)
(Initial value)
(Initial value)
(Initial value)

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