HD6417032F20V Renesas Electronics America, HD6417032F20V Datasheet - Page 418

• Manufacturer Part Number: HD6417032F20V
• Description: SH1 ROMLESS LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7030r

Specifications of HD6417032F20V

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 13 Serial Communication Interface (SCI)
Communication Formats: Four formats are available. Parity-bit settings are ignored when a
multiprocessor format is selected. For details see table 13.8.
Clock: See the description in the asynchronous mode section.
Transmitting Multiprocessor Serial Data: Figure 13.10 shows a sample flowchart for
transmitting multiprocessor serial data. The procedure for transmitting multiprocessor serial data is
listed below.
1. SCI initialization: select the TxD pin function with the PFC.
2. SCI status check and transmit data write: read the serial status register (SSR), check that the
3. To continue transmitting serial data: read the TDRE bit to check whether it is safe to write (1);
4. To output a break signal at the end of serial transmission: set the DR bit to 0 (I/O data port
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REJ09B0272-0700
Figure 13.9 Example of Communication between Processors Using Multiprocessor Format
TDRE bit is 1, then write transmit data in the transmit data register (TDR). Also set MPBT
(multiprocessor bit transfer) to 0 or 1 in SSR. Finally, clear TDRE to 0.
if so, write data in TDR, then clear TDRE to 0. When the DMAC is started by a transmit-data-
empty interrupt request (TXI) to write data in TDR, the TDRE bit is checked and cleared
automatically.
register), then clear TE to 0 in SCR and set the TxD pin function as output port with the PFC.
Serial
MPB: multiprocessor bit
data
Transmitting
processor A
processor
Receiving
(ID = 01)
receiving processor address
(Sending Data H'AA to Receiving Processor A)
ID-sending cycle:
H'01
processor B
Receiving
(MPB = 1)
(ID = 02)
Serial communication line
processor specified by ID
data sent to receiving
Data-sending cycle:
processor C
Receiving
(ID = 03)
H'AA
(MPB = 0)
processor D
Receiving
(ID = 04)