HD6417032F20V Renesas Electronics America, HD6417032F20V Datasheet - Page 435

• Manufacturer Part Number: HD6417032F20V
• Description: SH1 ROMLESS LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7030r

Specifications of HD6417032F20V

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

13.4
The SCI has four interrupt sources in each channel: transmit-end (TEI), receive-error (ERI),
receive-data-full (RXI), and transmit-data-empty (TXI). Table 13.12 lists the interrupt sources and
indicates their priority. These interrupts can be enabled and disabled by the TIE, RIE, and TEIE
bits in the serial control register (SCR). Each interrupt request is sent separately to the interrupt
controller.
TXI is requested when the TDRE bit in SSR is set to 1. TXI can start the direct memory access
controller (DMAC) to transfer data. TDRE is automatically cleared to 0 when the DMAC executes
a data transfer to the transmit data register (TDR).
RXI is requested when the RDRF bit in SSR is set to 1. RXI can start the DMAC to transfer data.
RDRF is automatically cleared to 0 when the DMAC executes a data transfer to the receive data
register (RDR). ERI is requested when the ORER, PER, or FER bit in SSR is set to 1. ERI cannot
start the DMAC.
TEI is requested when the TEND bit in SSR is set to 1. TEI cannot start the DMAC. A TXI
interrupt indicates that transmit data writing is enabled. A TEI interrupt indicates that the transmit
operation is complete.
Table 13.12 SCI Interrupt Sources
Interrupt Source
ERI
RXI
TXI
TEI
13.5
Note the following points when using the SCI.
TDR Write and TDRE Flags: The TDRE bit in the serial status register (SSR) is a status flag
indicating loading of transmit data from TDR into TSR. The SCI sets TDRE to 1 when it transfers
data from TDR to TSR. Data can be written in TDR regardless of the status of the TDRE bit. If
new data is written in TDR when TDRE is 0, the old data stored in TDR will be lost because this
data has not yet been transferred to TSR. Before writing transmit data to TDR, be sure to check
that TDRE is set to 1.
SCI Interrupt Sources and the DMAC
Usage Notes
Description
Receive error (ORER, PER, or FER)
Receive data full (RDRF)
Transmit data empty (TDRE)
Transmit end (TEND)
Section 13 Serial Communication Interface (SCI)
Rev. 7.00 Jan 31, 2006 page 407 of 658
DMAC Activation
No
Yes
Yes
No
REJ09B0272-0700
Priority
Low
High