SX28AC/SS Parallax Inc, SX28AC/SS Datasheet - Page 32

• Manufacturer Part Number: SX28AC/SS
• Description: IC MCU 2K FLASH 50MHZ 28SSOP
• Manufacturer: Parallax Inc
• Series: SXr

Specifications of SX28AC/SS

• Core Processor: RISC
• Core Size: 8-Bit
• Speed: 75MHz
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 20
• Program Memory Size: 3KB (2K x 12)
• Program Memory Type: FLASH
• Ram Size: 136 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 28-SSOP
• Product: Microcontroller Basic Stamps
• Flash: 2 KBytes
• Timers: 8 bit
• Operating Supply Voltage: 3 to 5.5 V
• Eeprom Size: -
• Data Converters: -
• Connectivity: -
• Lead Free Status / Rohs Status: No RoHS Version Available

Parallax SX20AC/SX28AC
15.4. RAM Addressing
Direct Addressing
The FSR register must initialized with an appropriate
value in order to address the desired RAM register. The
following table and code example show how to directly
access the banked registers.
mov
clr
mov
clr
Indirect Addressing
To access any register via indirect addressing, simply
move the eight-bit address of the desired register into the
FSR and use INDF as the operand. The example below
shows how to clear all RAM locations from 10h to 1Fh in
all eight banks:
clr
:loop setb SFR.4 ;set bit 4: addr 10h-1Fh,
clr
incsz
jmp
15.5.
Often it is desirable to set the bank select bits of the FSR
register in one instruction cycle. The Bank instruction
provides this capability. This instruction sets the upper
bits of the FSR to point to a specific RAM bank without
affecting the other FSR bits. Example:
bank
inc
15.6.
The instruction set contains instructions to set, reset, and
test individual bits in data memory. The device is capable
of bit addressing anywhere in data memory.
© Parallax Inc.
FSR,#$070
$010
FSR,#$D0
$010
FSR
INDF
FSR
:loop
The Bank Instruction
$F0
$1F
Bit Manipulation
Bank
0
1
2
3
4
5
6
7
;clear FSR to 00h (at addr 04h)
;30-3Fh, etc
;clear register pointed to by
;FSR
;increment FSR and test, skip
;jmp if 00h
;jump back and clear next
;register
;Select Bank 7 in FSR
;increment file register
;1Fh in Bank 7
;Select RAM Bank 3
;Clear register 10h on
;Bank 3
;Select RAM Bank 6
;Clear register 10h on
;Bank 6
FSR Value
0D0h
010h
030h
050h
070h
090h
0B0h
0F0h
Page 32 of 51
15.7.
The device contains three registers associated with each
I/O port. The first register (Data Direction Register),
configures each port pin as a Hi-Z input or output. The
second register (TTL/CMOS Register), selects the desired
input level for the input. The third register (Pull-Up
Register), enables a weak pull-up resistor on the pin
configured as a input. In addition to using the associated
port registers, appropriate values must be written into the
MODE register to configure the I/O ports.
When two successive read-modify-write instructions are
used on the same I/O port with a very high clock rate, the
“write” part of one instruction might not occur soon
enough before the “read” part of the very next instruction,
resulting in getting “old” data for the second instruction.
To ensure predictable results, avoid using two successive
read-modify-write instructions that access the same port
data register if the clock rate is high.
15.8.
The bank of 31 registers serves as a set of accumulators.
The instruction set contains instructions to increment and
decrement the register file. The device also includes both
INCSZ fr (increment file register and skip if zero) and
DECSZ fr (decrement file register and skip if zero)
instructions.
15.9.
Testing
The device has specific instructions to facilitate loop
counting. The DECSZ fr (decrement file register and skip
if zero) tests any one of the file registers and skips the
next instruction (which can be a branch back to loop) if
the result is zero.
15.10. Branch and Loop Call Instructions
The device contains an 8-level hardware stack where the
return address is stored when a subroutine is called.
Multiple stack levels allow subroutine nesting. The
instruction set supports absolute address branching.
Input/Output Operation
Increment/Decrement
Loop Counting and Data Pointing
Rev 1.6 11/20/2006
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