SX28AC/SS Parallax Inc, SX28AC/SS Datasheet - Page 35

• Manufacturer Part Number: SX28AC/SS
• Description: IC MCU 2K FLASH 50MHZ 28SSOP
• Manufacturer: Parallax Inc
• Series: SXr

Specifications of SX28AC/SS

• Core Processor: RISC
• Core Size: 8-Bit
• Speed: 75MHz
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 20
• Program Memory Size: 3KB (2K x 12)
• Program Memory Type: FLASH
• Ram Size: 136 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 28-SSOP
• Product: Microcontroller Basic Stamps
• Flash: 2 KBytes
• Timers: 8 bit
• Operating Supply Voltage: 3 to 5.5 V
• Eeprom Size: -
• Data Converters: -
• Connectivity: -
• Lead Free Status / Rohs Status: No RoHS Version Available

Parallax SX20AC/SX28AC
16.0 NATIVE SX INSTRUCTION SET SUMMARY TABLES
Table 16-1 through Table 16-6 list all of the native
assembly instructions, organized by category. For each
instruction, the table shows the instruction mnemonic (as
written in assembly language), a brief description of what
the instruction does, the number of instruction cycles
required for execution, the binary opcode, and the status
bits affected by the instruction.
The “Clock Cycles (Turbo)” column typically shows a
value of 1, which means that the overall throughput for
the instruction is one per clock cycle. Exceptions include
program control branch instructions, which take 3 clock
cycles, and the system control instruction IREAD, which
takes 4.
© Parallax Inc.
AND fr,W
AND W,fr
AND W,#lit
NOT fr
OR fr,W
OR W,fr
OR w,#lit
XOR fr,W
XOR W,fr
XOR W,#lit
Mnemonic,
Operands
AND of fr and W into fr (fr = fr & W)
AND of W and fr into W (W = W & fr)
AND of W and Literal into W (W = W &b lit)
Complement of fr into fr (fr = fr ^ FFh)
OR of fr and W into fr (fr = fr | W)
OR of W and fr in to fr (W – W | fr)
Or of W and Literal into W (W = W | lit)
XOR of fr and W into fr (fr = fr ^ W)
XOR of W and fr into W (W = W ^ fr)
XOR of W and Literal into W (W = W ^ lit)
Table 16-1:
Description
Native
SX Instruction Set: Logical Operands
Page 35 of 51
Clock Cycles
(Slow Mode)
In some cases, the exact number of cycles depends on the
outcome of the instruction (such as the test-and-skip
instructions) or the clocking mode (Slow or Turbo). In
those cases, all possible numbers of cycles are shown in
the table. The instruction execution time is derived by
dividing the oscillator frequency by either one (Turbo
mode) or four (Slow). The divide-by factor is selected
through the FUSE Word register.
A superset of these instructions are available in the SASM
assembler of the SX-Key IDE, and supported by the SX
Key User’s Manual . Both are available for free download
from www.parallax.com/sx.
4
4
4
4
4
4
4
4
4
4
Clock Cycles
(Turbo)
1
1
1
1
1
1
1
1
1
1
0001 011f ffff
0001 010f ffff
1110 kkkk kkkk
0010 011f ffff
0001 001f ffff
0001 000f ffff
1101 kkkk kkkk
0001 101f ffff
0001 100f ffff
1111 kkkk kkkk
Opcode
Rev 1.6 11/20/2006
www.parallax.com
Affected
Bits
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z