HD6413007F20 Renesas Electronics America, HD6413007F20 Datasheet - Page 137
HD6413007F20
Manufacturer Part Number
HD6413007F20
Description
IC H8 MCU ROMLESS 5V 100QFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Datasheet
1.D13007F20V.pdf
(798 pages)
Specifications of HD6413007F20
Core Processor
H8/300H
Core Size
16-Bit
Speed
20MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, PWM, WDT
Number Of I /o
35
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
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Manufacturer
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Price
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6.1
The H8/3006 and H8/3007 have an on-chip bus controller (BSC) that manages the external
address space divided into eight areas. The bus specifications, such as bus width and number of
access states, can be set independently for each area, enabling multiple memories to be connected
easily.
The bus controller also has a bus arbitration function that controls the operation of the internal bus
masters-the CPU, DMA controller (DMAC), and DRAM interface and can release the bus to an
external device.
6.1.1
The features of the bus controller are listed below.
• Manages external address space in area units
• Basic bus interface
• DRAM interface
⎯ Manages the external space as eight areas (0 to 7) of 128 kbytes in 1M-byte modes, or 2
⎯ Bus specifications can be set independently for each area
⎯ DRAM/burst ROM interfaces can be set
⎯ Chip select (CS
⎯ 8-bit access or 16-bit access can be selected for each area
⎯ Two-state access or three-state access can be selected for each area
⎯ Program wait states can be inserted for each area
⎯ Pin wait insertion capability is provided
⎯ DRAM interface can be set for areas 2 to 5
⎯ Row address/column address multiplexed output (8/9/10 bits)
⎯ 2-CAS byte access mode
⎯ Burst operation (fast page mode)
⎯ T
⎯ Choice of CAS-before-RAS refreshing or self-refreshing
Mbytes in 16-Mbyte modes
P
Overview
Features
cycle insertion to secure RAS precharging time
0
to CS
Section 6 Bus Controller
7
) can be output for areas 0 to 7
Rev.5.00 Sep. 12, 2007 Page 107 of 764
REJ09B0396-0500
6. Bus Controller
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