HD6413007F20 Renesas Electronics America, HD6413007F20 Datasheet - Page 263
HD6413007F20
Manufacturer Part Number
HD6413007F20
Description
IC H8 MCU ROMLESS 5V 100QFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Datasheet
1.D13007F20V.pdf
(798 pages)
Specifications of HD6413007F20
Core Processor
H8/300H
Core Size
16-Bit
Speed
20MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, PWM, WDT
Number Of I /o
35
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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7.4.9
The DMAC channel priority order is: channel 0 > channel 1 and channel A > channel B.
Table 7.12 shows the complete priority order.
Table 7.12 Channel Priority Order
Short Address Mode
Channel 0A
Channel 0B
Channel 1A
Channel 1B
If transfers are requested on two or more channels simultaneously, or if a transfer on one channel
is requested during a transfer on another channel, the DMAC operates as follows.
• When a transfer is requested, the DMAC requests the bus right. When it gets the bus right, it
• Once a transfer starts on one channel, requests to other channels are held pending until that
• After each transfer in short address mode, and each externally-requested or cycle-steal transfer
• After completion of a burst-mode transfer, or after transfer of one block in block transfer
Figure 7.19 shows the timing when channel 0A is set up for I/O mode and channel 1 for burst
mode, and a transfer request for channel 0A is received while channel 1 is active.
starts a transfer on the highest-priority channel at that time.
channel releases the bus.
in normal mode, the DMAC releases the bus and returns to step 1. After releasing the bus, if
there is a transfer request for another channel, the DMAC requests the bus again.
mode, the DMAC releases the bus and returns to step 1. If there is a transfer request for a
higher-priority channel or a bus request from a higher-priority bus master, however, the
DMAC releases the bus after completing the transfer of the current byte or word. After
releasing the bus, if there is a transfer request for another channel, the DMAC requests the bus
again.
Multiple-Channel Operation
Full Address Mode
Channel 0
Channel 1
Rev.5.00 Sep. 12, 2007 Page 233 of 764
Priority
High
Low
7. DMA Controller
REJ09B0396-0500
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